led.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_TH_RESULT" "led:inst\|count\[0\] rst clk -2.985 ns register " "Info: th for register \"led:inst\|count\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is -2.985 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] 2 REG LC_X8_Y13_N6 16 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N6; Fanout = 16; REG Node = 'lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns led:inst\|count\[0\] 3 REG LC_X48_Y22_N5 12 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X48_Y22_N5; Fanout = 12; REG Node = 'led:inst\|count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[0] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.730 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_122 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 13; PIN Node = 'rst'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 136 120 288 152 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.486 ns) + CELL(0.442 ns) 9.397 ns led:inst\|count\[0\]~257 2 COMB LC_X48_Y22_N7 3 " "Info: 2: + IC(7.486 ns) + CELL(0.442 ns) = 9.397 ns; Loc. = LC_X48_Y22_N7; Fanout = 3; COMB Node = 'led:inst\|count\[0\]~257'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.928 ns" { rst led:inst|count[0]~257 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.867 ns) 10.730 ns led:inst\|count\[0\] 3 REG LC_X48_Y22_N5 12 " "Info: 3: + IC(0.466 ns) + CELL(0.867 ns) = 10.730 ns; Loc. = LC_X48_Y22_N5; Fanout = 12; REG Node = 'led:inst\|count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { led:inst|count[0]~257 led:inst|count[0] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 25.89 % ) " "Info: Total cell delay = 2.778 ns ( 25.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.952 ns ( 74.11 % ) " "Info: Total interconnect delay = 7.952 ns ( 74.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.730 ns" { rst led:inst|count[0]~257 led:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.730 ns" { rst {} rst~out0 {} led:inst|count[0]~257 {} led:inst|count[0] {} } { 0.000ns 0.000ns 7.486ns 0.466ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[0] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.730 ns" { rst led:inst|count[0]~257 led:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.730 ns" { rst {} rst~out0 {} led:inst|count[0]~257 {} led:inst|count[0] {} } { 0.000ns 0.000ns 7.486ns 0.466ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 11:32:59 2008 " "Info: Processing ended: Wed Apr 23 11:32:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}