prev_cmp_led.map.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 07:41:14 2008 " "Info: Processing started: Wed Apr 09 07:41:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led -c led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/lpm_counter0.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/lpm_counter0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led-one " "Info: Found design unit 1: led-one" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myled.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file myled.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 myled " "Info: Found entity 1: myled" {  } { { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "myled " "Info: Elaborating entity \"myled\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:inst " "Info: Elaborating entity \"led\" for hierarchy \"led:inst\"" {  } { { "myled.bdf" "inst" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 96 304 400 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst1 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst1\"" {  } { { "myled.bdf" "inst1" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 0 280 424 64 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/lecture/embed/FPGA/FPGAExample/led/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qeh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_qeh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qeh " "Info: Found entity 1: cntr_qeh" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_qeh lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated " "Info: Elaborating entity \"cntr_qeh\" for hierarchy \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|myled\|led:inst\|present 4 " "Info: State machine \"\|myled\|led:inst\|present\" contains 4 states" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|myled\|led:inst\|present " "Info: Selected Auto state machine encoding method for state machine \"\|myled\|led:inst\|present\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|myled\|led:inst\|present " "Info: Encoding result for state machine \"\|myled\|led:inst\|present\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led:inst\|present.s3 " "Info: Encoded state bit \"led:inst\|present.s3\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led:inst\|present.s2 " "Info: Encoded state bit \"led:inst\|present.s2\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led:inst\|present.s1 " "Info: Encoded state bit \"led:inst\|present.s1\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "led:inst\|present.s0 " "Info: Encoded state bit \"led:inst\|present.s0\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myled\|led:inst\|present.s0 0000 " "Info: State \"\|myled\|led:inst\|present.s0\" uses code string \"0000\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myled\|led:inst\|present.s1 0011 " "Info: State \"\|myled\|led:inst\|present.s1\" uses code string \"0011\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myled\|led:inst\|present.s2 0101 " "Info: State \"\|myled\|led:inst\|present.s2\" uses code string \"0101\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|myled\|led:inst\|present.s3 1001 " "Info: State \"\|myled\|led:inst\|present.s3\" uses code string \"1001\"" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 11 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led:inst\|count\[3\] data_in GND " "Warning (14130): Reduced register \"led:inst\|count\[3\]\" with stuck data_in port to stuck value GND" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\] " "Info: Register \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\] " "Info: Register \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "76 " "Info: Implemented 76 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "66 " "Info: Implemented 66 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Allocated 165 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 07:41:17 2008 " "Info: Processing ended: Wed Apr 09 07:41:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}