📄 led.sim.rpt
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; |led|lpm_add_sub:Add0|addcore:adder|_~0 ; |led|lpm_add_sub:Add0|addcore:adder|_~0 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~3 ; |led|lpm_add_sub:Add0|addcore:adder|_~3 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~8 ; |led|lpm_add_sub:Add0|addcore:adder|_~8 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~9 ; |led|lpm_add_sub:Add0|addcore:adder|_~9 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~11 ; |led|lpm_add_sub:Add0|addcore:adder|_~11 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~12 ; |led|lpm_add_sub:Add0|addcore:adder|_~12 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~14 ; |led|lpm_add_sub:Add0|addcore:adder|_~14 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~15 ; |led|lpm_add_sub:Add0|addcore:adder|_~15 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |led|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout ;
+--------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |led|present~2 ; |led|present~2 ; out ;
; |led|present~3 ; |led|present~3 ; out ;
; |led|count[3] ; |led|count[3] ; regout ;
; |led|rst ; |led|rst ; out ;
; |led|present~7 ; |led|present~7 ; out0 ;
; |led|Selector0~9 ; |led|Selector0~9 ; out0 ;
; |led|Selector14~8 ; |led|Selector14~8 ; out0 ;
; |led|Selector15~8 ; |led|Selector15~8 ; out0 ;
; |led|Equal0~9 ; |led|Equal0~9 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~1 ; |led|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~2 ; |led|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~4 ; |led|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~5 ; |led|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~6 ; |led|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~7 ; |led|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~10 ; |led|lpm_add_sub:Add0|addcore:adder|_~10 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~13 ; |led|lpm_add_sub:Add0|addcore:adder|_~13 ; out0 ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |led|present~2 ; |led|present~2 ; out ;
; |led|present~3 ; |led|present~3 ; out ;
; |led|count[3] ; |led|count[3] ; regout ;
; |led|Selector14~8 ; |led|Selector14~8 ; out0 ;
; |led|Selector15~8 ; |led|Selector15~8 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~1 ; |led|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~2 ; |led|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |led|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; |led|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~4 ; |led|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~5 ; |led|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~6 ; |led|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~7 ; |led|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~10 ; |led|lpm_add_sub:Add0|addcore:adder|_~10 ; out0 ;
; |led|lpm_add_sub:Add0|addcore:adder|_~13 ; |led|lpm_add_sub:Add0|addcore:adder|_~13 ; out0 ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue Apr 01 07:55:41 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off led -c led
Info: Using vector source file "D:/lecture/embed/FPGA/FPGAExample/led/led.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 85.19 %
Info: Number of transitions in simulation is 6494
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 98 megabytes of memory during processing
Info: Processing ended: Tue Apr 01 07:55:43 2008
Info: Elapsed time: 00:00:02
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