led.map.rpt

FPGA和VHDL的全过程和源码

; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; lpm_counter0.vhd                 ; yes             ; User VHDL File                     ; D:/lecture/embed/FPGA/FPGAExample/led/lpm_counter0.vhd               ;
; led.vhd                          ; yes             ; User VHDL File                     ; D:/lecture/embed/FPGA/FPGAExample/led/led.vhd                        ;
; myled.bdf                        ; yes             ; User Block Diagram/Schematic File  ; D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf                      ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc           ;
; db/cntr_qeh.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf                ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 66    ;
;     -- Combinational with no register       ; 27    ;
;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 37    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 27    ;
;     -- 3 input functions                    ; 8     ;
;     -- 2 input functions                    ; 27    ;
;     -- 1 input functions                    ; 2     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 43    ;
;     -- arithmetic mode                      ; 23    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 12    ;
;                                             ;       ;
; Total registers                             ; 39    ;
; Total logic cells in carry chains           ; 24    ;
; I/O pins                                    ; 10    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 252   ;
; Average fan-out                             ; 3.32  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                  ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                 ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
; |myled                                    ; 66 (0)      ; 39           ; 0           ; 10   ; 0            ; 27 (0)       ; 2 (0)             ; 37 (0)           ; 24 (0)          ; 0 (0)      ; |myled                                                                              ; work         ;
;    |led:inst|                             ; 42 (42)     ; 15           ; 0           ; 0    ; 0            ; 27 (27)      ; 2 (2)             ; 13 (13)          ; 0 (0)           ; 0 (0)      ; |myled|led:inst                                                                     ; work         ;
;    |lpm_counter0:inst1|                   ; 24 (0)      ; 24           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 24 (0)           ; 24 (0)          ; 0 (0)      ; |myled|lpm_counter0:inst1                                                           ; work         ;
;       |lpm_counter:lpm_counter_component| ; 24 (0)      ; 24           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 24 (0)           ; 24 (0)          ; 0 (0)      ; |myled|lpm_counter0:inst1|lpm_counter:lpm_counter_component                         ; work         ;
;          |cntr_qeh:auto_generated|        ; 24 (24)     ; 24           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 24 (24)          ; 24 (24)         ; 0 (0)      ; |myled|lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated ; work         ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+----------------------------------------------------------------+
; State Machine - |myled|led:inst|present                        ;
+------------+------------+------------+------------+------------+
; Name       ; present.s3 ; present.s2 ; present.s1 ; present.s0 ;
+------------+------------+------------+------------+------------+
; present.s0 ; 0          ; 0          ; 0          ; 0          ;
; present.s1 ; 0          ; 0          ; 1          ; 1          ;
; present.s2 ; 0          ; 1          ; 0          ; 1          ;
; present.s3 ; 1          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                   ;
+---------------------------------------------------------------------------------------------+----------------------------------------+
; Register name                                                                               ; Reason for Removal                     ;
+---------------------------------------------------------------------------------------------+----------------------------------------+
; lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[24..25] ; Lost fanout                            ;
; led:inst|count[3]                                                                           ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 3                                                       ;                                        ;
+---------------------------------------------------------------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;