jp4x4.hier_info

FPGA和VHDL的全过程和源码

|jp4x4_test
kbrow[0] <= jp4x4:inst.kbrow[0]
kbrow[1] <= jp4x4:inst.kbrow[1]
kbrow[2] <= jp4x4:inst.kbrow[2]
kbrow[3] <= jp4x4:inst.kbrow[3]
clk => lpm_counter0:inst4.clock
start => jp4x4:inst.start
kbcol[0] => jp4x4:inst.kbcol[0]
kbcol[1] => jp4x4:inst.kbcol[1]
kbcol[2] => jp4x4:inst.kbcol[2]
kbcol[3] => jp4x4:inst.kbcol[3]
scan[0] <= jp4x4:inst.scan[0]
scan[1] <= jp4x4:inst.scan[1]
scan[2] <= jp4x4:inst.scan[2]
scan[3] <= jp4x4:inst.scan[3]
seg7_out[0] <= jp4x4:inst.seg7_out[0]
seg7_out[1] <= jp4x4:inst.seg7_out[1]
seg7_out[2] <= jp4x4:inst.seg7_out[2]
seg7_out[3] <= jp4x4:inst.seg7_out[3]
seg7_out[4] <= jp4x4:inst.seg7_out[4]
seg7_out[5] <= jp4x4:inst.seg7_out[5]
seg7_out[6] <= jp4x4:inst.seg7_out[6]


|jp4x4_test|jp4x4:inst
clk => count[1].CLK
clk => count[0].CLK
clk => kbrow[3]~reg0.CLK
clk => kbrow[2]~reg0.CLK
clk => kbrow[1]~reg0.CLK
clk => kbrow[0]~reg0.CLK
clk => sta[1].CLK
clk => sta[0].CLK
clk => seg7[6].CLK
clk => seg7[5].CLK
clk => seg7[4].CLK
clk => seg7[3].CLK
clk => seg7[2].CLK
clk => seg7[1].CLK
clk => seg7[0].CLK
clk => dat[4].CLK
clk => dat[3].CLK
clk => dat[2].CLK
clk => dat[1].CLK
clk => dat[0].CLK
start => seg7[6].PRESET
start => seg7[5].PRESET
start => seg7[4].PRESET
start => seg7[3].PRESET
start => seg7[2].PRESET
start => seg7[1].PRESET
start => seg7[0].PRESET
start => dat[4].PRESET
start => dat[3].ACLR
start => dat[2].ACLR
start => dat[1].ACLR
start => dat[0].ACLR
kbcol[0] => Mux16.IN19
kbcol[0] => Mux15.IN19
kbcol[0] => Mux14.IN19
kbcol[0] => Mux13.IN19
kbcol[0] => Mux12.IN19
kbcol[0] => Mux11.IN19
kbcol[0] => Mux10.IN19
kbcol[0] => Mux9.IN19
kbcol[0] => Mux8.IN19
kbcol[0] => Mux7.IN19
kbcol[0] => Mux6.IN19
kbcol[0] => Mux5.IN19
kbcol[0] => Mux4.IN19
kbcol[1] => Mux16.IN18
kbcol[1] => Mux15.IN18
kbcol[1] => Mux14.IN18
kbcol[1] => Mux13.IN18
kbcol[1] => Mux12.IN18
kbcol[1] => Mux11.IN18
kbcol[1] => Mux10.IN18
kbcol[1] => Mux9.IN18
kbcol[1] => Mux8.IN18
kbcol[1] => Mux7.IN18
kbcol[1] => Mux6.IN18
kbcol[1] => Mux5.IN18
kbcol[1] => Mux4.IN18
kbcol[2] => Mux16.IN17
kbcol[2] => Mux15.IN17
kbcol[2] => Mux14.IN17
kbcol[2] => Mux13.IN17
kbcol[2] => Mux12.IN17
kbcol[2] => Mux11.IN17
kbcol[2] => Mux10.IN17
kbcol[2] => Mux9.IN17
kbcol[2] => Mux8.IN17
kbcol[2] => Mux7.IN17
kbcol[2] => Mux6.IN17
kbcol[2] => Mux5.IN17
kbcol[2] => Mux4.IN17
kbcol[3] => Mux16.IN16
kbcol[3] => Mux15.IN16
kbcol[3] => Mux14.IN16
kbcol[3] => Mux13.IN16
kbcol[3] => Mux12.IN16
kbcol[3] => Mux11.IN16
kbcol[3] => Mux10.IN16
kbcol[3] => Mux9.IN16
kbcol[3] => Mux8.IN16
kbcol[3] => Mux7.IN16
kbcol[3] => Mux6.IN16
kbcol[3] => Mux5.IN16
kbcol[3] => Mux4.IN16
kbrow[0] <= kbrow[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kbrow[1] <= kbrow[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kbrow[2] <= kbrow[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
kbrow[3] <= kbrow[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[0] <= seg7_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[1] <= seg7_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[2] <= seg7_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[3] <= seg7_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[4] <= seg7_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[5] <= seg7_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seg7_out[6] <= seg7_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
scan[0] <= <VCC>
scan[1] <= <GND>
scan[2] <= <GND>
scan[3] <= <GND>


|jp4x4_test|lpm_counter0:inst4
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]
q[12] <= lpm_counter:lpm_counter_component.q[12]
q[13] <= lpm_counter:lpm_counter_component.q[13]
q[14] <= lpm_counter:lpm_counter_component.q[14]
q[15] <= lpm_counter:lpm_counter_component.q[15]
q[16] <= lpm_counter:lpm_counter_component.q[16]
q[17] <= lpm_counter:lpm_counter_component.q[17]
q[18] <= lpm_counter:lpm_counter_component.q[18]
q[19] <= lpm_counter:lpm_counter_component.q[19]
q[20] <= lpm_counter:lpm_counter_component.q[20]
q[21] <= lpm_counter:lpm_counter_component.q[21]
q[22] <= lpm_counter:lpm_counter_component.q[22]
q[23] <= lpm_counter:lpm_counter_component.q[23]
q[24] <= lpm_counter:lpm_counter_component.q[24]
q[25] <= lpm_counter:lpm_counter_component.q[25]


|jp4x4_test|lpm_counter0:inst4|lpm_counter:lpm_counter_component
clock => cntr_qeh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
data[19] => ~NO_FANOUT~
data[20] => ~NO_FANOUT~
data[21] => ~NO_FANOUT~
data[22] => ~NO_FANOUT~
data[23] => ~NO_FANOUT~
data[24] => ~NO_FANOUT~
data[25] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_qeh:auto_generated.q[0]
q[1] <= cntr_qeh:auto_generated.q[1]
q[2] <= cntr_qeh:auto_generated.q[2]
q[3] <= cntr_qeh:auto_generated.q[3]
q[4] <= cntr_qeh:auto_generated.q[4]
q[5] <= cntr_qeh:auto_generated.q[5]
q[6] <= cntr_qeh:auto_generated.q[6]
q[7] <= cntr_qeh:auto_generated.q[7]
q[8] <= cntr_qeh:auto_generated.q[8]
q[9] <= cntr_qeh:auto_generated.q[9]
q[10] <= cntr_qeh:auto_generated.q[10]
q[11] <= cntr_qeh:auto_generated.q[11]
q[12] <= cntr_qeh:auto_generated.q[12]
q[13] <= cntr_qeh:auto_generated.q[13]
q[14] <= cntr_qeh:auto_generated.q[14]
q[15] <= cntr_qeh:auto_generated.q[15]
q[16] <= cntr_qeh:auto_generated.q[16]
q[17] <= cntr_qeh:auto_generated.q[17]
q[18] <= cntr_qeh:auto_generated.q[18]
q[19] <= cntr_qeh:auto_generated.q[19]
q[20] <= cntr_qeh:auto_generated.q[20]
q[21] <= cntr_qeh:auto_generated.q[21]
q[22] <= cntr_qeh:auto_generated.q[22]
q[23] <= cntr_qeh:auto_generated.q[23]
q[24] <= cntr_qeh:auto_generated.q[24]
q[25] <= cntr_qeh:auto_generated.q[25]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|jp4x4_test|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
clock => counter_cella17.CLK
clock => counter_cella18.CLK
clock => counter_cella19.CLK
clock => counter_cella20.CLK
clock => counter_cella21.CLK
clock => counter_cella22.CLK
clock => counter_cella23.CLK
clock => counter_cella24.CLK
clock => counter_cella25.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
q[17] <= counter_cella17.REGOUT
q[18] <= counter_cella18.REGOUT
q[19] <= counter_cella19.REGOUT
q[20] <= counter_cella20.REGOUT
q[21] <= counter_cella21.REGOUT
q[22] <= counter_cella22.REGOUT
q[23] <= counter_cella23.REGOUT
q[24] <= counter_cella24.REGOUT
q[25] <= counter_cella25.REGOUT