prev_cmp_jp4x4.qmsg

FPGA和VHDL的全过程和源码

{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[3\] GND " "Warning (13410): Pin \"scan\[3\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[2\] GND " "Warning (13410): Pin \"scan\[2\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[1\] GND " "Warning (13410): Pin \"scan\[1\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[0\] VCC " "Warning (13410): Pin \"scan\[0\]\" stuck at VCC" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "18 18 " "Info: 18 registers lost all their fanouts during netlist optimizations. The first 18 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[8\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[9\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[10\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[11\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[12\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[13\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[14\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[15\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[16\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[17\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[18\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[19\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[20\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[21\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[22\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "76 " "Info: Implemented 76 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "55 " "Info: Implemented 55 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Allocated 164 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 21:55:03 2008 " "Info: Processing ended: Sun Apr 20 21:55:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 20 21:55:04 2008 " "Info: Processing started: Sun Apr 20 21:55:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off jp4x4 -c jp4x4 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jp4x4 -c jp4x4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "jp4x4 EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"jp4x4\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "76 Top " "Info: Previous placement does not exist for 76 of 76 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}