jp4x4.map.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qeh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_qeh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qeh " "Info: Found entity 1: cntr_qeh" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_qeh lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated " "Info: Elaborating entity \"cntr_qeh\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "jp4x4:inst\|sta\[0\] jp4x4:inst\|count\[0\] " "Info: Duplicate register \"jp4x4:inst\|sta\[0\]\" merged to single register \"jp4x4:inst\|count\[0\]\", power-up level changed" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 29 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[3\] GND " "Warning (13410): Pin \"scan\[3\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[2\] GND " "Warning (13410): Pin \"scan\[2\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[1\] GND " "Warning (13410): Pin \"scan\[1\]\" stuck at GND" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[0\] VCC " "Warning (13410): Pin \"scan\[0\]\" stuck at VCC" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "22 22 " "Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[4\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[5\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[6\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[8\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[9\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[10\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[11\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[12\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[13\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[14\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[15\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[16\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[17\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[18\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[19\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[20\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[21\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[22\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\] " "Info: Register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "72 " "Info: Implemented 72 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "51 " "Info: Implemented 51 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Allocated 165 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 21:57:09 2008 " "Info: Processing ended: Sun Apr 20 21:57:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}