jp4x4.fnsim.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux5\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux6\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux7 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux7\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux8 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux8\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux9 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux9\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux10 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux10\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux11 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux11\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux12 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux12\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 62 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux13 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux13\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 62 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux14 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux14\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux15 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux15\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux16 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux16\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux17 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux17\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux24 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux24\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_mux:Mux25 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_mux:Mux25\"" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 11:59:39 2008 " "Info: Processing ended: Sun Apr 20 11:59:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}