jp4x4.fnsim.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 20 11:59:35 2008 " "Info: Processing started: Sun Apr 20 11:59:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jp4x4 -c jp4x4 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jp4x4 -c jp4x4 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jp4x4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jp4x4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jp4x4-one " "Info: Found design unit 1: jp4x4-one" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jp4x4 " "Info: Found entity 1: jp4x4" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jp4x4_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file jp4x4_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 jp4x4_test " "Info: Found entity 1: jp4x4_test" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jp4x4_test " "Info: Elaborating entity \"jp4x4_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jp4x4 jp4x4:inst " "Info: Elaborating entity \"jp4x4\" for hierarchy \"jp4x4:inst\"" {  } { { "jp4x4_test.bdf" "inst" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 96 288 464 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst4 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst4\"" {  } { { "jp4x4_test.bdf" "inst4" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 8 304 448 72 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qeh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_qeh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qeh " "Info: Found entity 1: cntr_qeh" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_qeh lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated " "Info: Elaborating entity \"cntr_qeh\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "27 " "Info: Inferred 27 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "jp4x4:inst\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"jp4x4:inst\|Add0\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux0\"" {  } { { "jp4x4.vhd" "Mux0" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 30 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux1\"" {  } { { "jp4x4.vhd" "Mux1" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 30 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux2\"" {  } { { "jp4x4.vhd" "Mux2" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 30 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux3\"" {  } { { "jp4x4.vhd" "Mux3" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 30 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux4\"" {  } { { "jp4x4.vhd" "Mux4" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux5\"" {  } { { "jp4x4.vhd" "Mux5" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux6\"" {  } { { "jp4x4.vhd" "Mux6" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux7\"" {  } { { "jp4x4.vhd" "Mux7" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux8\"" {  } { { "jp4x4.vhd" "Mux8" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux9\"" {  } { { "jp4x4.vhd" "Mux9" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux10\"" {  } { { "jp4x4.vhd" "Mux10" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux11\"" {  } { { "jp4x4.vhd" "Mux11" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 54 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux12\"" {  } { { "jp4x4.vhd" "Mux12" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 62 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux13\"" {  } { { "jp4x4.vhd" "Mux13" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 62 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux14 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux14\"" {  } { { "jp4x4.vhd" "Mux14" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux15 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux15\"" {  } { { "jp4x4.vhd" "Mux15" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux16\"" {  } { { "jp4x4.vhd" "Mux16" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 70 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux17\"" {  } { { "jp4x4.vhd" "Mux17" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux18\"" {  } { { "jp4x4.vhd" "Mux18" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux19\"" {  } { { "jp4x4.vhd" "Mux19" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux20 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux20\"" {  } { { "jp4x4.vhd" "Mux20" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux21 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux21\"" {  } { { "jp4x4.vhd" "Mux21" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux22 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux22\"" {  } { { "jp4x4.vhd" "Mux22" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux23 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux23\"" {  } { { "jp4x4.vhd" "Mux23" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux24 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux24\"" {  } { { "jp4x4.vhd" "Mux24" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "jp4x4:inst\|Mux25 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"jp4x4:inst\|Mux25\"" {  } { { "jp4x4.vhd" "Mux25" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jp4x4:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_add_sub:Add0\"" {  } { { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 76 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "jp4x4:inst\|lpm_add_sub:Add0\|addcore:adder jp4x4:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"jp4x4:inst\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"jp4x4:inst\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}