prev_cmp_jp4x4.map.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 20 21:54:59 2008 " "Info: Processing started: Sun Apr 20 21:54:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jp4x4 -c jp4x4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jp4x4 -c jp4x4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_counter0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_counter0-SYN " "Info: Found design unit 1: lpm_counter0-SYN" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jp4x4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jp4x4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jp4x4-one " "Info: Found design unit 1: jp4x4-one" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jp4x4 " "Info: Found entity 1: jp4x4" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jp4x4_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file jp4x4_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 jp4x4_test " "Info: Found entity 1: jp4x4_test" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jp4x4_test " "Info: Elaborating entity \"jp4x4_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jp4x4 jp4x4:inst " "Info: Elaborating entity \"jp4x4\" for hierarchy \"jp4x4:inst\"" {  } { { "jp4x4_test.bdf" "inst" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 96 288 464 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst4 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst4\"" {  } { { "jp4x4_test.bdf" "inst4" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 8 304 448 72 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.vhd" "lpm_counter_component" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/lpm_counter0.vhd" 73 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}