prev_cmp_jp4x4.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[4\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[4\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[3\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[3\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[1\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[1\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "jp4x4:inst\|fn~34 " "Info: Detected gated clock \"jp4x4:inst\|fn~34\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|fn~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[0\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[0\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[2\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[2\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "jp4x4:inst\|fn~3 " "Info: Detected gated clock \"jp4x4:inst\|fn~3\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|fn~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] " "Info: Detected ripple clock \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]\" as buffer" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register jp4x4:inst\|sta\[1\] jp4x4:inst\|seg7\[4\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"jp4x4:inst\|sta\[1\]\" and destination register \"jp4x4:inst\|seg7\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.347 ns + Longest register register " "Info: + Longest register to register delay is 2.347 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jp4x4:inst\|sta\[1\] 1 REG LC_X7_Y17_N3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y17_N3; Fanout = 15; REG Node = 'jp4x4:inst\|sta\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|sta[1] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.317 ns) + CELL(0.114 ns) 1.431 ns jp4x4:inst\|Mux19~13 2 COMB LC_X8_Y17_N2 1 " "Info: 2: + IC(1.317 ns) + CELL(0.114 ns) = 1.431 ns; Loc. = LC_X8_Y17_N2; Fanout = 1; COMB Node = 'jp4x4:inst\|Mux19~13'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.431 ns" { jp4x4:inst|sta[1] jp4x4:inst|Mux19~13 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.478 ns) 2.347 ns jp4x4:inst\|seg7\[4\] 3 REG LC_X8_Y17_N6 1 " "Info: 3: + IC(0.438 ns) + CELL(0.478 ns) = 2.347 ns; Loc. = LC_X8_Y17_N6; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { jp4x4:inst|Mux19~13 jp4x4:inst|seg7[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.592 ns ( 25.22 % ) " "Info: Total cell delay = 0.592 ns ( 25.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.755 ns ( 74.78 % ) " "Info: Total interconnect delay = 1.755 ns ( 74.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.347 ns" { jp4x4:inst|sta[1] jp4x4:inst|Mux19~13 jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.347 ns" { jp4x4:inst|sta[1] {} jp4x4:inst|Mux19~13 {} jp4x4:inst|seg7[4] {} } { 0.000ns 1.317ns 0.438ns } { 0.000ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.791 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] 2 REG LC_X8_Y13_N7 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.645 ns) + CELL(0.711 ns) 7.791 ns jp4x4:inst\|seg7\[4\] 3 REG LC_X8_Y17_N6 1 " "Info: 3: + IC(3.645 ns) + CELL(0.711 ns) = 7.791 ns; Loc. = LC_X8_Y17_N6; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.356 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.98 % ) " "Info: Total cell delay = 3.115 ns ( 39.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.676 ns ( 60.02 % ) " "Info: Total interconnect delay = 4.676 ns ( 60.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.791 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] 2 REG LC_X8_Y13_N7 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.645 ns) + CELL(0.711 ns) 7.791 ns jp4x4:inst\|sta\[1\] 3 REG LC_X7_Y17_N3 15 " "Info: 3: + IC(3.645 ns) + CELL(0.711 ns) = 7.791 ns; Loc. = LC_X7_Y17_N3; Fanout = 15; REG Node = 'jp4x4:inst\|sta\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.356 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|sta[1] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.98 % ) " "Info: Total cell delay = 3.115 ns ( 39.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.676 ns ( 60.02 % ) " "Info: Total interconnect delay = 4.676 ns ( 60.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|sta[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|sta[1] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|sta[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|sta[1] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.347 ns" { jp4x4:inst|sta[1] jp4x4:inst|Mux19~13 jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.347 ns" { jp4x4:inst|sta[1] {} jp4x4:inst|Mux19~13 {} jp4x4:inst|seg7[4] {} } { 0.000ns 1.317ns 0.438ns } { 0.000ns 0.114ns 0.478ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|sta[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|sta[1] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { jp4x4:inst|seg7[4] {} } {  } {  } "" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "jp4x4:inst\|seg7\[0\] jp4x4:inst\|seg7_out\[0\] clk 4.656 ns " "Info: Found hold time violation between source  pin or register \"jp4x4:inst\|seg7\[0\]\" and destination pin or register \"jp4x4:inst\|seg7_out\[0\]\" for clock \"clk\" (Hold time is 4.656 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.744 ns + Largest " "Info: + Largest clock skew is 6.744 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.535 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 14.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] 2 REG LC_X8_Y13_N7 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.645 ns) + CELL(0.935 ns) 8.015 ns jp4x4:inst\|dat\[3\] 3 REG LC_X7_Y17_N4 1 " "Info: 3: + IC(3.645 ns) + CELL(0.935 ns) = 8.015 ns; Loc. = LC_X7_Y17_N4; Fanout = 1; REG Node = 'jp4x4:inst\|dat\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.580 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|dat[3] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.442 ns) 8.985 ns jp4x4:inst\|fn~34 4 COMB LC_X7_Y17_N2 1 " "Info: 4: + IC(0.528 ns) + CELL(0.442 ns) = 8.985 ns; Loc. = LC_X7_Y17_N2; Fanout = 1; COMB Node = 'jp4x4:inst\|fn~34'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.970 ns" { jp4x4:inst|dat[3] jp4x4:inst|fn~34 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.292 ns) 9.714 ns jp4x4:inst\|fn~3 5 COMB LC_X7_Y17_N9 7 " "Info: 5: + IC(0.437 ns) + CELL(0.292 ns) = 9.714 ns; Loc. = LC_X7_Y17_N9; Fanout = 7; COMB Node = 'jp4x4:inst\|fn~3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { jp4x4:inst|fn~34 jp4x4:inst|fn~3 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.110 ns) + CELL(0.711 ns) 14.535 ns jp4x4:inst\|seg7_out\[0\] 6 REG LC_X13_Y18_N2 1 " "Info: 6: + IC(4.110 ns) + CELL(0.711 ns) = 14.535 ns; Loc. = LC_X13_Y18_N2; Fanout = 1; REG Node = 'jp4x4:inst\|seg7_out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.821 ns" { jp4x4:inst|fn~3 jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.784 ns ( 32.91 % ) " "Info: Total cell delay = 4.784 ns ( 32.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.751 ns ( 67.09 % ) " "Info: Total interconnect delay = 9.751 ns ( 67.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.535 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.535 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns 0.528ns 0.437ns 4.110ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.442ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.791 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] 2 REG LC_X8_Y13_N7 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.645 ns) + CELL(0.711 ns) 7.791 ns jp4x4:inst\|seg7\[0\] 3 REG LC_X8_Y17_N4 1 " "Info: 3: + IC(3.645 ns) + CELL(0.711 ns) = 7.791 ns; Loc. = LC_X8_Y17_N4; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.356 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 39.98 % ) " "Info: Total cell delay = 3.115 ns ( 39.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.676 ns ( 60.02 % ) " "Info: Total interconnect delay = 4.676 ns ( 60.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.535 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.535 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns 0.528ns 0.437ns 4.110ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.442ns 0.292ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.879 ns - Shortest register register " "Info: - Shortest register to register delay is 1.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jp4x4:inst\|seg7\[0\] 1 REG LC_X8_Y17_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y17_N4; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|seg7[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.309 ns) 1.879 ns jp4x4:inst\|seg7_out\[0\] 2 REG LC_X13_Y18_N2 1 " "Info: 2: + IC(1.570 ns) + CELL(0.309 ns) = 1.879 ns; Loc. = LC_X13_Y18_N2; Fanout = 1; REG Node = 'jp4x4:inst\|seg7_out\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { jp4x4:inst|seg7[0] jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 16.44 % ) " "Info: Total cell delay = 0.309 ns ( 16.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.570 ns ( 83.56 % ) " "Info: Total interconnect delay = 1.570 ns ( 83.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { jp4x4:inst|seg7[0] jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.879 ns" { jp4x4:inst|seg7[0] {} jp4x4:inst|seg7_out[0] {} } { 0.000ns 1.570ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.535 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.535 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns 0.528ns 0.437ns 4.110ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.442ns 0.292ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.791 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] jp4x4:inst|seg7[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.791 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] {} jp4x4:inst|seg7[0] {} } { 0.000ns 0.000ns 1.031ns 3.645ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.879 ns" { jp4x4:inst|seg7[0] jp4x4:inst|seg7_out[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.879 ns" { jp4x4:inst|seg7[0] {} jp4x4:inst|seg7_out[0] {} } { 0.000ns 1.570ns } { 0.000ns 0.309ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}