jp4x4.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "jp4x4:inst\|seg7\[4\] jp4x4:inst\|seg7_out\[4\] clk 5.891 ns " "Info: Found hold time violation between source  pin or register \"jp4x4:inst\|seg7\[4\]\" and destination pin or register \"jp4x4:inst\|seg7_out\[4\]\" for clock \"clk\" (Hold time is 5.891 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.377 ns + Largest " "Info: + Largest clock skew is 7.377 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.426 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] 2 REG LC_X8_Y13_N3 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.903 ns) + CELL(0.935 ns) 8.273 ns jp4x4:inst\|dat\[3\] 3 REG LC_X42_Y20_N3 1 " "Info: 3: + IC(3.903 ns) + CELL(0.935 ns) = 8.273 ns; Loc. = LC_X42_Y20_N3; Fanout = 1; REG Node = 'jp4x4:inst\|dat\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.838 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|dat[3] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.114 ns) 8.903 ns jp4x4:inst\|fn~34 4 COMB LC_X42_Y20_N5 1 " "Info: 4: + IC(0.516 ns) + CELL(0.114 ns) = 8.903 ns; Loc. = LC_X42_Y20_N5; Fanout = 1; COMB Node = 'jp4x4:inst\|fn~34'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.630 ns" { jp4x4:inst|dat[3] jp4x4:inst|fn~34 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.292 ns) 9.917 ns jp4x4:inst\|fn~3 5 COMB LC_X41_Y20_N8 7 " "Info: 5: + IC(0.722 ns) + CELL(0.292 ns) = 9.917 ns; Loc. = LC_X41_Y20_N8; Fanout = 7; COMB Node = 'jp4x4:inst\|fn~3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.014 ns" { jp4x4:inst|fn~34 jp4x4:inst|fn~3 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.798 ns) + CELL(0.711 ns) 15.426 ns jp4x4:inst\|seg7_out\[4\] 6 REG LC_X45_Y20_N2 1 " "Info: 6: + IC(4.798 ns) + CELL(0.711 ns) = 15.426 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst\|seg7_out\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.509 ns" { jp4x4:inst|fn~3 jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.456 ns ( 28.89 % ) " "Info: Total cell delay = 4.456 ns ( 28.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.970 ns ( 71.11 % ) " "Info: Total interconnect delay = 10.970 ns ( 71.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.426 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.426 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns 0.516ns 0.722ns 4.798ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.049 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 8.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] 2 REG LC_X8_Y13_N3 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.903 ns) + CELL(0.711 ns) 8.049 ns jp4x4:inst\|seg7\[4\] 3 REG LC_X41_Y20_N4 1 " "Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X41_Y20_N4; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.70 % ) " "Info: Total cell delay = 3.115 ns ( 38.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.934 ns ( 61.30 % ) " "Info: Total interconnect delay = 4.934 ns ( 61.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.426 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.426 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns 0.516ns 0.722ns 4.798ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.277 ns - Shortest register register " "Info: - Shortest register to register delay is 1.277 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jp4x4:inst\|seg7\[4\] 1 REG LC_X41_Y20_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y20_N4; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|seg7[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.115 ns) 1.277 ns jp4x4:inst\|seg7_out\[4\] 2 REG LC_X45_Y20_N2 1 " "Info: 2: + IC(1.162 ns) + CELL(0.115 ns) = 1.277 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst\|seg7_out\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { jp4x4:inst|seg7[4] jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 9.01 % ) " "Info: Total cell delay = 0.115 ns ( 9.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 90.99 % ) " "Info: Total interconnect delay = 1.162 ns ( 90.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { jp4x4:inst|seg7[4] jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.277 ns" { jp4x4:inst|seg7[4] {} jp4x4:inst|seg7_out[4] {} } { 0.000ns 1.162ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.426 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|dat[3] jp4x4:inst|fn~34 jp4x4:inst|fn~3 jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.426 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|dat[3] {} jp4x4:inst|fn~34 {} jp4x4:inst|fn~3 {} jp4x4:inst|seg7_out[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns 0.516ns 0.722ns 4.798ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[4] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { jp4x4:inst|seg7[4] jp4x4:inst|seg7_out[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.277 ns" { jp4x4:inst|seg7[4] {} jp4x4:inst|seg7_out[4] {} } { 0.000ns 1.162ns } { 0.000ns 0.115ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "jp4x4:inst\|seg7\[5\] kbcol\[1\] clk 6.214 ns register " "Info: tsu for register \"jp4x4:inst\|seg7\[5\]\" (data pin = \"kbcol\[1\]\", clock pin = \"clk\") is 6.214 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.226 ns + Longest pin register " "Info: + Longest pin to register delay is 14.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns kbcol\[1\] 1 PIN PIN_5 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_5; Fanout = 13; PIN Node = 'kbcol\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { kbcol[1] } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 104 272 168 "kbcol\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.136 ns) + CELL(0.442 ns) 11.047 ns jp4x4:inst\|Mux5~37 2 COMB LC_X39_Y20_N8 1 " "Info: 2: + IC(9.136 ns) + CELL(0.442 ns) = 11.047 ns; Loc. = LC_X39_Y20_N8; Fanout = 1; COMB Node = 'jp4x4:inst\|Mux5~37'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.578 ns" { kbcol[1] jp4x4:inst|Mux5~37 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.081 ns) + CELL(0.590 ns) 12.718 ns jp4x4:inst\|Mux18~13 3 COMB LC_X41_Y20_N9 1 " "Info: 3: + IC(1.081 ns) + CELL(0.590 ns) = 12.718 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; COMB Node = 'jp4x4:inst\|Mux18~13'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.671 ns" { jp4x4:inst|Mux5~37 jp4x4:inst|Mux18~13 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.309 ns) 14.226 ns jp4x4:inst\|seg7\[5\] 4 REG LC_X42_Y20_N9 1 " "Info: 4: + IC(1.199 ns) + CELL(0.309 ns) = 14.226 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.810 ns ( 19.75 % ) " "Info: Total cell delay = 2.810 ns ( 19.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.416 ns ( 80.25 % ) " "Info: Total interconnect delay = 11.416 ns ( 80.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.226 ns" { kbcol[1] jp4x4:inst|Mux5~37 jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.226 ns" { kbcol[1] {} kbcol[1]~out0 {} jp4x4:inst|Mux5~37 {} jp4x4:inst|Mux18~13 {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 9.136ns 1.081ns 1.199ns } { 0.000ns 1.469ns 0.442ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.049 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] 2 REG LC_X8_Y13_N3 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.903 ns) + CELL(0.711 ns) 8.049 ns jp4x4:inst\|seg7\[5\] 3 REG LC_X42_Y20_N9 1 " "Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.70 % ) " "Info: Total cell delay = 3.115 ns ( 38.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.934 ns ( 61.30 % ) " "Info: Total interconnect delay = 4.934 ns ( 61.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.226 ns" { kbcol[1] jp4x4:inst|Mux5~37 jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.226 ns" { kbcol[1] {} kbcol[1]~out0 {} jp4x4:inst|Mux5~37 {} jp4x4:inst|Mux18~13 {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 9.136ns 1.081ns 1.199ns } { 0.000ns 1.469ns 0.442ns 0.590ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}