jp4x4.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[4\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[4\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[3\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[3\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[1\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[1\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "jp4x4:inst\|fn~34 " "Info: Detected gated clock \"jp4x4:inst\|fn~34\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|fn~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[2\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[2\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jp4x4:inst\|dat\[0\] " "Info: Detected ripple clock \"jp4x4:inst\|dat\[0\]\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|dat\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "jp4x4:inst\|fn~3 " "Info: Detected gated clock \"jp4x4:inst\|fn~3\" as buffer" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 17 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jp4x4:inst\|fn~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] " "Info: Detected ripple clock \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]\" as buffer" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register jp4x4:inst\|count\[0\] jp4x4:inst\|seg7\[5\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"jp4x4:inst\|count\[0\]\" and destination register \"jp4x4:inst\|seg7\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.232 ns + Longest register register " "Info: + Longest register to register delay is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jp4x4:inst\|count\[0\] 1 REG LC_X41_Y20_N3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y20_N3; Fanout = 16; REG Node = 'jp4x4:inst\|count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|count[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.610 ns) + CELL(0.114 ns) 0.724 ns jp4x4:inst\|Mux18~13 2 COMB LC_X41_Y20_N9 1 " "Info: 2: + IC(0.610 ns) + CELL(0.114 ns) = 0.724 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; COMB Node = 'jp4x4:inst\|Mux18~13'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.724 ns" { jp4x4:inst|count[0] jp4x4:inst|Mux18~13 } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.309 ns) 2.232 ns jp4x4:inst\|seg7\[5\] 3 REG LC_X42_Y20_N9 1 " "Info: 3: + IC(1.199 ns) + CELL(0.309 ns) = 2.232 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.423 ns ( 18.95 % ) " "Info: Total cell delay = 0.423 ns ( 18.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.809 ns ( 81.05 % ) " "Info: Total interconnect delay = 1.809 ns ( 81.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { jp4x4:inst|count[0] jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { jp4x4:inst|count[0] {} jp4x4:inst|Mux18~13 {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.610ns 1.199ns } { 0.000ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.049 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] 2 REG LC_X8_Y13_N3 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.903 ns) + CELL(0.711 ns) 8.049 ns jp4x4:inst\|seg7\[5\] 3 REG LC_X42_Y20_N9 1 " "Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst\|seg7\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.70 % ) " "Info: Total cell delay = 3.115 ns ( 38.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.934 ns ( 61.30 % ) " "Info: Total interconnect delay = 4.934 ns ( 61.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.049 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 32 120 288 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\] 2 REG LC_X8_Y13_N3 20 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.903 ns) + CELL(0.711 ns) 8.049 ns jp4x4:inst\|count\[0\] 3 REG LC_X41_Y20_N3 16 " "Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X41_Y20_N3; Fanout = 16; REG Node = 'jp4x4:inst\|count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|count[0] } "NODE_NAME" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.70 % ) " "Info: Total cell delay = 3.115 ns ( 38.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.934 ns ( 61.30 % ) " "Info: Total interconnect delay = 4.934 ns ( 61.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|count[0] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|count[0] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { jp4x4:inst|count[0] jp4x4:inst|Mux18~13 jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { jp4x4:inst|count[0] {} jp4x4:inst|Mux18~13 {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.610ns 1.199ns } { 0.000ns 0.114ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|seg7[5] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.049 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] jp4x4:inst|count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.049 ns" { clk {} clk~out0 {} lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3] {} jp4x4:inst|count[0] {} } { 0.000ns 0.000ns 1.031ns 3.903ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jp4x4:inst|seg7[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { jp4x4:inst|seg7[5] {} } {  } {  } "" } } { "jp4x4.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.vhd" 42 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}