prev_cmp_jp4x4.fit.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.431 ns register register " "Info: Estimated most critical path is register to register delay of 2.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[0\] 1 REG LAB_X8_Y13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y13; Fanout = 3; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[0] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.575 ns) 1.035 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella0~COUTCOUT1 2 COMB LAB_X8_Y13 2 " "Info: 2: + IC(0.460 ns) + CELL(0.575 ns) = 1.035 ns; Loc. = LAB_X8_Y13; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella0~COUTCOUT1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.035 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[0] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella0~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.115 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella1~COUTCOUT1 3 COMB LAB_X8_Y13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.115 ns; Loc. = LAB_X8_Y13; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella0~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.195 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella2~COUTCOUT1 4 COMB LAB_X8_Y13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.195 ns; Loc. = LAB_X8_Y13; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.275 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella3~COUTCOUT1 5 COMB LAB_X8_Y13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.275 ns; Loc. = LAB_X8_Y13; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella3~COUTCOUT1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella3~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 54 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.533 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella4~COUT 6 COMB LAB_X8_Y13 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.533 ns; Loc. = LAB_X8_Y13; Fanout = 3; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|counter_cella4~COUT'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella3~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella4~COUT } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.431 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\] 7 REG LAB_X8_Y13 20 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.431 ns; Loc. = LAB_X8_Y13; Fanout = 20; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jp4x4/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns ( 81.08 % ) " "Info: Total cell delay = 1.971 ns ( 81.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.460 ns ( 18.92 % ) " "Info: Total interconnect delay = 0.460 ns ( 18.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.431 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[0] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella0~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella3~COUTCOUT1 lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X0_Y14 X9_Y27 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y14 to location X9_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[3\] GND " "Info: Pin scan\[3\] has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { scan[3] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan\[3\]" } } } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[2\] GND " "Info: Pin scan\[2\] has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { scan[2] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan\[2\]" } } } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[1\] GND " "Info: Pin scan\[1\] has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { scan[1] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan\[1\]" } } } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[0\] VCC " "Info: Pin scan\[0\] has VCC driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { scan[0] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "scan\[0\]" } } } } { "jp4x4_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4_test.bdf" { { 152 480 656 168 "scan\[3..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { scan[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.fit.smsg " "Info: Generated suppressed messages file D:/lecture/embed/FPGA/FPGAExample/jp4x4/jp4x4.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "179 " "Info: Allocated 179 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 21:55:10 2008 " "Info: Processing ended: Sun Apr 20 21:55:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}