jp4x4.tan.rpt

FPGA和VHDL的全过程和源码

    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.232 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y20_N3; Fanout = 16; REG Node = 'jp4x4:inst|count[0]'
            Info: 2: + IC(0.610 ns) + CELL(0.114 ns) = 0.724 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; COMB Node = 'jp4x4:inst|Mux18~13'
            Info: 3: + IC(1.199 ns) + CELL(0.309 ns) = 2.232 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|seg7[5]'
            Info: Total cell delay = 0.423 ns ( 18.95 % )
            Info: Total interconnect delay = 1.809 ns ( 81.05 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 8.049 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
                Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|seg7[5]'
                Info: Total cell delay = 3.115 ns ( 38.70 % )
                Info: Total interconnect delay = 4.934 ns ( 61.30 % )
            Info: - Longest clock path from clock "clk" to source register is 8.049 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
                Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X41_Y20_N3; Fanout = 16; REG Node = 'jp4x4:inst|count[0]'
                Info: Total cell delay = 3.115 ns ( 38.70 % )
                Info: Total interconnect delay = 4.934 ns ( 61.30 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "jp4x4:inst|seg7[4]" and destination pin or register "jp4x4:inst|seg7_out[4]" for clock "clk" (Hold time is 5.891 ns)
    Info: + Largest clock skew is 7.377 ns
        Info: + Longest clock path from clock "clk" to destination register is 15.426 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
            Info: 3: + IC(3.903 ns) + CELL(0.935 ns) = 8.273 ns; Loc. = LC_X42_Y20_N3; Fanout = 1; REG Node = 'jp4x4:inst|dat[3]'
            Info: 4: + IC(0.516 ns) + CELL(0.114 ns) = 8.903 ns; Loc. = LC_X42_Y20_N5; Fanout = 1; COMB Node = 'jp4x4:inst|fn~34'
            Info: 5: + IC(0.722 ns) + CELL(0.292 ns) = 9.917 ns; Loc. = LC_X41_Y20_N8; Fanout = 7; COMB Node = 'jp4x4:inst|fn~3'
            Info: 6: + IC(4.798 ns) + CELL(0.711 ns) = 15.426 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst|seg7_out[4]'
            Info: Total cell delay = 4.456 ns ( 28.89 % )
            Info: Total interconnect delay = 10.970 ns ( 71.11 % )
        Info: - Shortest clock path from clock "clk" to source register is 8.049 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
            Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X41_Y20_N4; Fanout = 1; REG Node = 'jp4x4:inst|seg7[4]'
            Info: Total cell delay = 3.115 ns ( 38.70 % )
            Info: Total interconnect delay = 4.934 ns ( 61.30 % )
    Info: - Micro clock to output delay of source is 0.224 ns
    Info: - Shortest register to register delay is 1.277 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y20_N4; Fanout = 1; REG Node = 'jp4x4:inst|seg7[4]'
        Info: 2: + IC(1.162 ns) + CELL(0.115 ns) = 1.277 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst|seg7_out[4]'
        Info: Total cell delay = 0.115 ns ( 9.01 % )
        Info: Total interconnect delay = 1.162 ns ( 90.99 % )
    Info: + Micro hold delay of destination is 0.015 ns
Info: tsu for register "jp4x4:inst|seg7[5]" (data pin = "kbcol[1]", clock pin = "clk") is 6.214 ns
    Info: + Longest pin to register delay is 14.226 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_5; Fanout = 13; PIN Node = 'kbcol[1]'
        Info: 2: + IC(9.136 ns) + CELL(0.442 ns) = 11.047 ns; Loc. = LC_X39_Y20_N8; Fanout = 1; COMB Node = 'jp4x4:inst|Mux5~37'
        Info: 3: + IC(1.081 ns) + CELL(0.590 ns) = 12.718 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; COMB Node = 'jp4x4:inst|Mux18~13'
        Info: 4: + IC(1.199 ns) + CELL(0.309 ns) = 14.226 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|seg7[5]'
        Info: Total cell delay = 2.810 ns ( 19.75 % )
        Info: Total interconnect delay = 11.416 ns ( 80.25 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.049 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
        Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X42_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|seg7[5]'
        Info: Total cell delay = 3.115 ns ( 38.70 % )
        Info: Total interconnect delay = 4.934 ns ( 61.30 % )
Info: tco from clock "clk" to destination pin "seg7_out[4]" through register "jp4x4:inst|seg7_out[4]" is 21.269 ns
    Info: + Longest clock path from clock "clk" to source register is 15.426 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
        Info: 3: + IC(3.903 ns) + CELL(0.935 ns) = 8.273 ns; Loc. = LC_X42_Y20_N3; Fanout = 1; REG Node = 'jp4x4:inst|dat[3]'
        Info: 4: + IC(0.516 ns) + CELL(0.114 ns) = 8.903 ns; Loc. = LC_X42_Y20_N5; Fanout = 1; COMB Node = 'jp4x4:inst|fn~34'
        Info: 5: + IC(0.722 ns) + CELL(0.292 ns) = 9.917 ns; Loc. = LC_X41_Y20_N8; Fanout = 7; COMB Node = 'jp4x4:inst|fn~3'
        Info: 6: + IC(4.798 ns) + CELL(0.711 ns) = 15.426 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst|seg7_out[4]'
        Info: Total cell delay = 4.456 ns ( 28.89 % )
        Info: Total interconnect delay = 10.970 ns ( 71.11 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.619 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X45_Y20_N2; Fanout = 1; REG Node = 'jp4x4:inst|seg7_out[4]'
        Info: 2: + IC(3.495 ns) + CELL(2.124 ns) = 5.619 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'seg7_out[4]'
        Info: Total cell delay = 2.124 ns ( 37.80 % )
        Info: Total interconnect delay = 3.495 ns ( 62.20 % )
Info: th for register "jp4x4:inst|dat[1]" (data pin = "kbcol[3]", clock pin = "clk") is -2.449 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.049 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N3; Fanout = 20; REG Node = 'lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[3]'
        Info: 3: + IC(3.903 ns) + CELL(0.711 ns) = 8.049 ns; Loc. = LC_X39_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|dat[1]'
        Info: Total cell delay = 3.115 ns ( 38.70 % )
        Info: Total interconnect delay = 4.934 ns ( 61.30 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 10.513 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 13; PIN Node = 'kbcol[3]'
        Info: 2: + IC(8.735 ns) + CELL(0.309 ns) = 10.513 ns; Loc. = LC_X39_Y20_N9; Fanout = 1; REG Node = 'jp4x4:inst|dat[1]'
        Info: Total cell delay = 1.778 ns ( 16.91 % )
        Info: Total interconnect delay = 8.735 ns ( 83.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sun Apr 20 21:57:25 2008
    Info: Elapsed time: 00:00:02