jp4x4.tan.summary

FPGA和VHDL的全过程和源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.214 ns
From           : kbcol[1]
To             : jp4x4:inst|seg7[5]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.269 ns
From           : jp4x4:inst|seg7_out[4]
To             : seg7_out[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.449 ns
From           : kbcol[3]
To             : jp4x4:inst|dat[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : jp4x4:inst|count[0]
To             : jp4x4:inst|seg7[5]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : jp4x4:inst|seg7[4]
To             : jp4x4:inst|seg7_out[4]
From Clock     : clk
To Clock       : clk
Failed Paths   : 7

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 7

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