prev_cmp_jiao_tong.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0:inst1\|altpll:altpll_component\"" {  } { { "altpll0.vhd" "altpll_component" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/altpll0.vhd" 128 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll0:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll0:inst1\|altpll:altpll_component\"" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/altpll0.vhd" 128 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "jiao_tong:inst\|r2 jiao_tong:inst\|r1 " "Info: Duplicate register \"jiao_tong:inst\|r2\" merged to single register \"jiao_tong:inst\|r1\", power-up level changed" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|jiao_tong_test\|jiao_tong:inst\|stx 4 " "Info: State machine \"\|jiao_tong_test\|jiao_tong:inst\|stx\" contains 4 states" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|jiao_tong_test\|jiao_tong:inst\|stx " "Info: Selected Auto state machine encoding method for state machine \"\|jiao_tong_test\|jiao_tong:inst\|stx\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|jiao_tong_test\|jiao_tong:inst\|stx " "Info: Encoding result for state machine \"\|jiao_tong_test\|jiao_tong:inst\|stx\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst\|stx.st4 " "Info: Encoded state bit \"jiao_tong:inst\|stx.st4\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst\|stx.st3 " "Info: Encoded state bit \"jiao_tong:inst\|stx.st3\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst\|stx.st2 " "Info: Encoded state bit \"jiao_tong:inst\|stx.st2\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiao_tong:inst\|stx.st1 " "Info: Encoded state bit \"jiao_tong:inst\|stx.st1\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiao_tong_test\|jiao_tong:inst\|stx.st1 0000 " "Info: State \"\|jiao_tong_test\|jiao_tong:inst\|stx.st1\" uses code string \"0000\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiao_tong_test\|jiao_tong:inst\|stx.st2 0011 " "Info: State \"\|jiao_tong_test\|jiao_tong:inst\|stx.st2\" uses code string \"0011\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiao_tong_test\|jiao_tong:inst\|stx.st3 0101 " "Info: State \"\|jiao_tong_test\|jiao_tong:inst\|stx.st3\" uses code string \"0101\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiao_tong_test\|jiao_tong:inst\|stx.st4 1001 " "Info: State \"\|jiao_tong_test\|jiao_tong:inst\|stx.st4\" uses code string \"1001\"" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jiao_tong:inst\|\\process2:count\[0\] jiao_tong:inst\|cnt\[0\] " "Info: Duplicate register \"jiao_tong:inst\|\\process2:count\[0\]\" merged to single register \"jiao_tong:inst\|cnt\[0\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "jiao_tong:inst\|cnt\[1\] data_in GND " "Warning (14130): Reduced register \"jiao_tong:inst\|cnt\[1\]\" with stuck data_in port to stuck value GND" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 181 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|scan\[1\] " "Warning: LATCH primitive \"jiao_tong:inst\|scan\[1\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|scan\[0\] " "Warning: LATCH primitive \"jiao_tong:inst\|scan\[0\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|data\[0\] " "Warning: LATCH primitive \"jiao_tong:inst\|data\[0\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|data\[1\] " "Warning: LATCH primitive \"jiao_tong:inst\|data\[1\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|data\[2\] " "Warning: LATCH primitive \"jiao_tong:inst\|data\[2\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "jiao_tong:inst\|data\[3\] " "Warning: LATCH primitive \"jiao_tong:inst\|data\[3\]\" is permanently enabled" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "135 " "Info: Implemented 135 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "117 " "Info: Implemented 117 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 27 07:21:34 2008 " "Info: Processing ended: Sun Apr 27 07:21:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 27 07:21:35 2008 " "Info: Processing started: Sun Apr 27 07:21:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}