jiao_tong.map.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 27 07:24:23 2008 " "Info: Processing started: Sun Apr 27 07:24:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jiao_tong -c jiao_tong " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiao_tong -c jiao_tong" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altpll0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altpll0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpll0-SYN " "Info: Found design unit 1: altpll0-SYN" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/altpll0.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/altpll0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiao_tong.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jiao_tong.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jiao_tong-onejt " "Info: Found design unit 1: jiao_tong-onejt" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 jiao_tong " "Info: Found entity 1: jiao_tong" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiao_tong_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file jiao_tong_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 jiao_tong_test " "Info: Found entity 1: jiao_tong_test" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jiao_tong_test " "Info: Elaborating entity \"jiao_tong_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jiao_tong jiao_tong:inst " "Info: Elaborating entity \"jiao_tong\" for hierarchy \"jiao_tong:inst\"" {  } { { "jiao_tong_test.bdf" "inst" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 224 296 416 416 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data jiao_tong.vhd(188) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(188): inferring latch(es) for signal or variable \"data\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "scan jiao_tong.vhd(188) " "Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(188): inferring latch(es) for signal or variable \"scan\", which holds its previous value in one or more paths through the process" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[0\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"scan\[0\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "scan\[1\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"scan\[1\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[0\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"data\[0\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[1\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"data\[1\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[2\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"data\[2\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data\[3\] jiao_tong.vhd(188) " "Info (10041): Inferred latch for \"data\[3\]\" at jiao_tong.vhd(188)" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 188 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst1 " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst1\"" {  } { { "jiao_tong_test.bdf" "inst1" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 24 224 464 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}