jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_TH_RESULT" "jiao_tong:inst\|ql\[3\] jin clk 0.422 ns register " "Info: th for register \"jiao_tong:inst\|ql\[3\]\" (data pin = \"jin\", clock pin = \"clk\") is 0.422 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 80 40 208 96 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.875 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c: