jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_TSU_RESULT" "jiao_tong:inst\|stx.st3 jin clk 0.885 ns register " "Info: tsu for register \"jiao_tong:inst\|stx.st3\" (data pin = \"jin\", clock pin = \"clk\") is 0.885 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.669 ns + Longest pin register " "Info: + Longest pin to register delay is 10.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns jin 1 PIN PIN_122 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 22; PIN Node = 'jin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 112 280 280 "jin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.775 ns) + CELL(0.292 ns) 8.536 ns jiao_tong:inst\|Selector18~38 2 COMB LC_X44_Y10_N4 2 " "Info: 2: + IC(6.775 ns) + CELL(0.292 ns) = 8.536 ns; Loc. = LC_X44_Y10_N4; Fanout = 2; COMB Node = 'jiao_tong:inst\|Selector18~38'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.067 ns" { jin jiao_tong:inst|Selector18~38 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.266 ns) + CELL(0.867 ns) 10.669 ns jiao_tong:inst\|stx.st3 3 REG LC_X43_Y11_N3 7 " "Info: 3: + IC(1.266 ns) + CELL(0.867 ns) = 10.669 ns; Loc. = LC_X43_Y11_N3; Fanout = 7; REG Node = 'jiao_tong:inst\|stx.st3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.133 ns" { jiao_tong:inst|Selector18~38 jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.628 ns ( 24.63 % ) " "Info: Total cell delay = 2.628 ns ( 24.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.041 ns ( 75.37 % ) " "Info: Total interconnect delay = 8.041 ns ( 75.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.669 ns" { jin jiao_tong:inst|Selector18~38 jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.669 ns" { jin {} jin~out0 {} jiao_tong:inst|Selector18~38 {} jiao_tong:inst|stx.st3 {} } { 0.000ns 0.000ns 6.775ns 1.266ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst1\|altpll:altpll_component\|_clk0 -2.054 ns - " "Info: - Offset between input clock \"clk\" and output clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 80 40 208 96 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.875 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.993 ns) + CELL(0.935 ns) 7.641 ns jiao_tong:inst\|clk1hz 3 REG LC_X8_Y13_N9 26 " "Info: 3: + IC(3.993 ns) + CELL(0.935 ns) = 7.641 ns; Loc. = LC_X8_Y13_N9; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 11.875 ns jiao_tong:inst\|stx.st3 4 REG LC_X43_Y11_N3 7 " "Info: 4: + IC(3.523 ns) + CELL(0.711 ns) = 11.875 ns; Loc. = LC_X43_Y11_N3; Fanout = 7; REG Node = 'jiao_tong:inst\|stx.st3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.234 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.73 % ) " "Info: Total cell delay = 2.581 ns ( 21.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.294 ns ( 78.27 % ) " "Info: Total interconnect delay = 9.294 ns ( 78.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.669 ns" { jin jiao_tong:inst|Selector18~38 jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.669 ns" { jin {} jin~out0 {} jiao_tong:inst|Selector18~38 {} jiao_tong:inst|stx.st3 {} } { 0.000ns 0.000ns 6.775ns 1.266ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[6\] jiao_tong:inst\|ql\[1\] 20.306 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[6\]\" through register \"jiao_tong:inst\|ql\[1\]\" is 20.306 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 80 40 208 96 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 11.875 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 11.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.993 ns) + CELL(0.935 ns) 7.641 ns jiao_tong:inst\|clk1hz 3 REG LC_X8_Y13_N9 26 " "Info: 3: + IC(3.993 ns) + CELL(0.935 ns) = 7.641 ns; Loc. = LC_X8_Y13_N9; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 11.875 ns jiao_tong:inst\|ql\[1\] 4 REG LC_X43_Y11_N6 6 " "Info: 4: + IC(3.523 ns) + CELL(0.711 ns) = 11.875 ns; Loc. = LC_X43_Y11_N6; Fanout = 6; REG Node = 'jiao_tong:inst\|ql\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.234 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|ql[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.73 % ) " "Info: Total cell delay = 2.581 ns ( 21.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.294 ns ( 78.27 % ) " "Info: Total interconnect delay = 9.294 ns ( 78.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|ql[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|ql[1] {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.261 ns + Longest register pin " "Info: + Longest register to pin delay is 10.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|ql\[1\] 1 REG LC_X43_Y11_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y11_N6; Fanout = 6; REG Node = 'jiao_tong:inst\|ql\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|ql[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.073 ns) + CELL(0.442 ns) 2.515 ns jiao_tong:inst\|Mux2~14 2 COMB LC_X45_Y11_N1 7 " "Info: 2: + IC(2.073 ns) + CELL(0.442 ns) = 2.515 ns; Loc. = LC_X45_Y11_N1; Fanout = 7; COMB Node = 'jiao_tong:inst\|Mux2~14'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.515 ns" { jiao_tong:inst|ql[1] jiao_tong:inst|Mux2~14 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 190 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.482 ns) + CELL(0.114 ns) 3.111 ns jiao_tong:inst\|Mux7~18 3 COMB LC_X45_Y11_N8 1 " "Info: 3: + IC(0.482 ns) + CELL(0.114 ns) = 3.111 ns; Loc. = LC_X45_Y11_N8; Fanout = 1; COMB Node = 'jiao_tong:inst\|Mux7~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.596 ns" { jiao_tong:inst|Mux2~14 jiao_tong:inst|Mux7~18 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.519 ns) + CELL(0.590 ns) 5.220 ns jiao_tong:inst\|seg7\[6\]~65 4 COMB LC_X43_Y10_N6 1 " "Info: 4: + IC(1.519 ns) + CELL(0.590 ns) = 5.220 ns; Loc. = LC_X43_Y10_N6; Fanout = 1; COMB Node = 'jiao_tong:inst\|seg7\[6\]~65'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.109 ns" { jiao_tong:inst|Mux7~18 jiao_tong:inst|seg7[6]~65 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.917 ns) + CELL(2.124 ns) 10.261 ns seg7\[6\] 5 PIN PIN_156 0 " "Info: 5: + IC(2.917 ns) + CELL(2.124 ns) = 10.261 ns; Loc. = PIN_156; Fanout = 0; PIN Node = 'seg7\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.041 ns" { jiao_tong:inst|seg7[6]~65 seg7[6] } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 432 608 280 "seg7\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.270 ns ( 31.87 % ) " "Info: Total cell delay = 3.270 ns ( 31.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.991 ns ( 68.13 % ) " "Info: Total interconnect delay = 6.991 ns ( 68.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.261 ns" { jiao_tong:inst|ql[1] jiao_tong:inst|Mux2~14 jiao_tong:inst|Mux7~18 jiao_tong:inst|seg7[6]~65 seg7[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.261 ns" { jiao_tong:inst|ql[1] {} jiao_tong:inst|Mux2~14 {} jiao_tong:inst|Mux7~18 {} jiao_tong:inst|seg7[6]~65 {} seg7[6] {} } { 0.000ns 2.073ns 0.482ns 1.519ns 2.917ns } { 0.000ns 0.442ns 0.114ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|ql[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|ql[1] {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.261 ns" { jiao_tong:inst|ql[1] jiao_tong:inst|Mux2~14 jiao_tong:inst|Mux7~18 jiao_tong:inst|seg7[6]~65 seg7[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.261 ns" { jiao_tong:inst|ql[1] {} jiao_tong:inst|Mux2~14 {} jiao_tong:inst|Mux7~18 {} jiao_tong:inst|seg7[6]~65 {} seg7[6] {} } { 0.000ns 2.073ns 0.482ns 1.519ns 2.917ns } { 0.000ns 0.442ns 0.114ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "jin ra 16.767 ns Longest " "Info: Longest tpd from source pin \"jin\" to destination pin \"ra\" is 16.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns jin 1 PIN PIN_122 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 22; PIN Node = 'jin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 112 280 280 "jin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.773 ns) + CELL(0.292 ns) 8.534 ns jiao_tong:inst\|ra~16 2 COMB LC_X44_Y10_N7 1 " "Info: 2: + IC(6.773 ns) + CELL(0.292 ns) = 8.534 ns; Loc. = LC_X44_Y10_N7; Fanout = 1; COMB Node = 'jiao_tong:inst\|ra~16'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.065 ns" { jin jiao_tong:inst|ra~16 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.109 ns) + CELL(2.124 ns) 16.767 ns ra 3 PIN PIN_59 0 " "Info: 3: + IC(6.109 ns) + CELL(2.124 ns) = 16.767 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'ra'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { jiao_tong:inst|ra~16 ra } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 280 432 608 296 "ra" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.885 ns ( 23.17 % ) " "Info: Total cell delay = 3.885 ns ( 23.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.882 ns ( 76.83 % ) " "Info: Total interconnect delay = 12.882 ns ( 76.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.767 ns" { jin jiao_tong:inst|ra~16 ra } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.767 ns" { jin {} jin~out0 {} jiao_tong:inst|ra~16 {} ra {} } { 0.000ns 0.000ns 6.773ns 6.109ns } { 0.000ns 1.469ns 0.292ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}