jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register jiao_tong:inst\|cnt\[0\] register jiao_tong:inst\|\\process2:count\[6\] 42.764 ns " "Info: Slack time is 42.764 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"jiao_tong:inst\|cnt\[0\]\" and destination register \"jiao_tong:inst\|\\process2:count\[6\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "138.2 MHz 7.236 ns " "Info: Fmax is 138.2 MHz (period= 7.236 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.835 ns + Largest register register " "Info: + Largest register to register requirement is 49.835 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 47.946 ns " "Info: + Latch edge is 47.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.096 ns + Largest " "Info: + Largest clock skew is 0.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 7.417 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 7.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.993 ns) + CELL(0.711 ns) 7.417 ns jiao_tong:inst\|\\process2:count\[6\] 3 REG LC_X8_Y13_N8 4 " "Info: 3: + IC(3.993 ns) + CELL(0.711 ns) = 7.417 ns; Loc. = LC_X8_Y13_N8; Fanout = 4; REG Node = 'jiao_tong:inst\|\\process2:count\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.704 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|\process2:count[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.19 % ) " "Info: Total cell delay = 1.646 ns ( 22.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.771 ns ( 77.81 % ) " "Info: Total interconnect delay = 5.771 ns ( 77.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 1.778ns 3.993ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 7.321 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 7.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.897 ns) + CELL(0.711 ns) 7.321 ns jiao_tong:inst\|cnt\[0\] 3 REG LC_X46_Y11_N0 11 " "Info: 3: + IC(3.897 ns) + CELL(0.711 ns) = 7.321 ns; Loc. = LC_X46_Y11_N0; Fanout = 11; REG Node = 'jiao_tong:inst\|cnt\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.608 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 181 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.48 % ) " "Info: Total cell delay = 1.646 ns ( 22.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.675 ns ( 77.52 % ) " "Info: Total interconnect delay = 5.675 ns ( 77.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|cnt[0] {} } { 0.000ns 1.778ns 3.897ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 1.778ns 3.993ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|cnt[0] {} } { 0.000ns 1.778ns 3.897ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 181 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 1.778ns 3.993ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|cnt[0] {} } { 0.000ns 1.778ns 3.897ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.071 ns - Longest register register " "Info: - Longest register to register delay is 7.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|cnt\[0\] 1 REG LC_X46_Y11_N0 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X46_Y11_N0; Fanout = 11; REG Node = 'jiao_tong:inst\|cnt\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 181 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.426 ns) + CELL(0.423 ns) 4.849 ns jiao_tong:inst\|Add1~136 2 COMB LC_X9_Y13_N0 2 " "Info: 2: + IC(4.426 ns) + CELL(0.423 ns) = 4.849 ns; Loc. = LC_X9_Y13_N0; Fanout = 2; COMB Node = 'jiao_tong:inst\|Add1~136'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.849 ns" { jiao_tong:inst|cnt[0] jiao_tong:inst|Add1~136 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.927 ns jiao_tong:inst\|Add1~138 3 COMB LC_X9_Y13_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 4.927 ns; Loc. = LC_X9_Y13_N1; Fanout = 2; COMB Node = 'jiao_tong:inst\|Add1~138'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { jiao_tong:inst|Add1~136 jiao_tong:inst|Add1~138 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 5.005 ns jiao_tong:inst\|Add1~140 4 COMB LC_X9_Y13_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 5.005 ns; Loc. = LC_X9_Y13_N2; Fanout = 2; COMB Node = 'jiao_tong:inst\|Add1~140'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { jiao_tong:inst|Add1~138 jiao_tong:inst|Add1~140 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 5.083 ns jiao_tong:inst\|Add1~144 5 COMB LC_X9_Y13_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 5.083 ns; Loc. = LC_X9_Y13_N3; Fanout = 2; COMB Node = 'jiao_tong:inst\|Add1~144'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { jiao_tong:inst|Add1~140 jiao_tong:inst|Add1~144 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 5.261 ns jiao_tong:inst\|Add1~146 6 COMB LC_X9_Y13_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 5.261 ns; Loc. = LC_X9_Y13_N4; Fanout = 3; COMB Node = 'jiao_tong:inst\|Add1~146'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { jiao_tong:inst|Add1~144 jiao_tong:inst|Add1~146 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 5.882 ns jiao_tong:inst\|Add1~147 7 COMB LC_X9_Y13_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 5.882 ns; Loc. = LC_X9_Y13_N5; Fanout = 1; COMB Node = 'jiao_tong:inst\|Add1~147'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { jiao_tong:inst|Add1~146 jiao_tong:inst|Add1~147 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.478 ns) 7.071 ns jiao_tong:inst\|\\process2:count\[6\] 8 REG LC_X8_Y13_N8 4 " "Info: 8: + IC(0.711 ns) + CELL(0.478 ns) = 7.071 ns; Loc. = LC_X8_Y13_N8; Fanout = 4; REG Node = 'jiao_tong:inst\|\\process2:count\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.189 ns" { jiao_tong:inst|Add1~147 jiao_tong:inst|\process2:count[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.934 ns ( 27.35 % ) " "Info: Total cell delay = 1.934 ns ( 27.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.137 ns ( 72.65 % ) " "Info: Total interconnect delay = 5.137 ns ( 72.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.071 ns" { jiao_tong:inst|cnt[0] jiao_tong:inst|Add1~136 jiao_tong:inst|Add1~138 jiao_tong:inst|Add1~140 jiao_tong:inst|Add1~144 jiao_tong:inst|Add1~146 jiao_tong:inst|Add1~147 jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.071 ns" { jiao_tong:inst|cnt[0] {} jiao_tong:inst|Add1~136 {} jiao_tong:inst|Add1~138 {} jiao_tong:inst|Add1~140 {} jiao_tong:inst|Add1~144 {} jiao_tong:inst|Add1~146 {} jiao_tong:inst|Add1~147 {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 4.426ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.711ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.417 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 1.778ns 3.993ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.321 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|cnt[0] {} } { 0.000ns 1.778ns 3.897ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.071 ns" { jiao_tong:inst|cnt[0] jiao_tong:inst|Add1~136 jiao_tong:inst|Add1~138 jiao_tong:inst|Add1~140 jiao_tong:inst|Add1~144 jiao_tong:inst|Add1~146 jiao_tong:inst|Add1~147 jiao_tong:inst|\process2:count[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.071 ns" { jiao_tong:inst|cnt[0] {} jiao_tong:inst|Add1~136 {} jiao_tong:inst|Add1~138 {} jiao_tong:inst|Add1~140 {} jiao_tong:inst|Add1~144 {} jiao_tong:inst|Add1~146 {} jiao_tong:inst|Add1~147 {} jiao_tong:inst|\process2:count[6] {} } { 0.000ns 4.426ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.711ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register jiao_tong:inst\|a register jiao_tong:inst\|a 1.039 ns " "Info: Minimum slack time is 1.039 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"jiao_tong:inst\|a\" and destination register \"jiao_tong:inst\|a\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.830 ns + Shortest register register " "Info: + Shortest register to register delay is 0.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|a 1 REG LC_X43_Y10_N0 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y10_N0; Fanout = 12; REG Node = 'jiao_tong:inst\|a'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|a } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.521 ns) + CELL(0.309 ns) 0.830 ns jiao_tong:inst\|a 2 REG LC_X43_Y10_N0 12 " "Info: 2: + IC(0.521 ns) + CELL(0.309 ns) = 0.830 ns; Loc. = LC_X43_Y10_N0; Fanout = 12; REG Node = 'jiao_tong:inst\|a'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { jiao_tong:inst|a jiao_tong:inst|a } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.23 % ) " "Info: Total cell delay = 0.309 ns ( 37.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.521 ns ( 62.77 % ) " "Info: Total interconnect delay = 0.521 ns ( 62.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { jiao_tong:inst|a jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { jiao_tong:inst|a {} jiao_tong:inst|a {} } { 0.000ns 0.521ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.875 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.993 ns) + CELL(0.935 ns) 7.641 ns jiao_tong:inst\|clk1hz 3 REG LC_X8_Y13_N9 26 " "Info: 3: + IC(3.993 ns) + CELL(0.935 ns) = 7.641 ns; Loc. = LC_X8_Y13_N9; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 11.875 ns jiao_tong:inst\|a 4 REG LC_X43_Y10_N0 12 " "Info: 4: + IC(3.523 ns) + CELL(0.711 ns) = 11.875 ns; Loc. = LC_X43_Y10_N0; Fanout = 12; REG Node = 'jiao_tong:inst\|a'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.234 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.73 % ) " "Info: Total cell delay = 2.581 ns ( 21.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.294 ns ( 78.27 % ) " "Info: Total interconnect delay = 9.294 ns ( 78.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 11.875 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 11.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X10_Y13_N3 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N3; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.993 ns) + CELL(0.935 ns) 7.641 ns jiao_tong:inst\|clk1hz 3 REG LC_X8_Y13_N9 26 " "Info: 3: + IC(3.993 ns) + CELL(0.935 ns) = 7.641 ns; Loc. = LC_X8_Y13_N9; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.928 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.523 ns) + CELL(0.711 ns) 11.875 ns jiao_tong:inst\|a 4 REG LC_X43_Y10_N0 12 " "Info: 4: + IC(3.523 ns) + CELL(0.711 ns) = 11.875 ns; Loc. = LC_X43_Y10_N0; Fanout = 12; REG Node = 'jiao_tong:inst\|a'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.234 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.73 % ) " "Info: Total cell delay = 2.581 ns ( 21.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.294 ns ( 78.27 % ) " "Info: Total interconnect delay = 9.294 ns ( 78.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { jiao_tong:inst|a jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { jiao_tong:inst|a {} jiao_tong:inst|a {} } { 0.000ns 0.521ns } { 0.000ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|a } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.875 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|a {} } { 0.000ns 1.778ns 3.993ns 3.523ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}