prev_cmp_jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_TSU_RESULT" "jiao_tong:inst\|qh\[0\] jin clk 5.716 ns register " "Info: tsu for register \"jiao_tong:inst\|qh\[0\]\" (data pin = \"jin\", clock pin = \"clk\") is 5.716 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.599 ns + Longest pin register " "Info: + Longest pin to register delay is 15.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns jin 1 PIN PIN_122 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 22; PIN Node = 'jin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 112 280 280 "jin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(10.359 ns) + CELL(0.442 ns) 12.270 ns jiao_tong:inst\|qh\[3\]~780 2 COMB LC_X17_Y22_N2 4 " "Info: 2: + IC(10.359 ns) + CELL(0.442 ns) = 12.270 ns; Loc. = LC_X17_Y22_N2; Fanout = 4; COMB Node = 'jiao_tong:inst\|qh\[3\]~780'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.801 ns" { jin jiao_tong:inst|qh[3]~780 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.462 ns) + CELL(0.867 ns) 15.599 ns jiao_tong:inst\|qh\[0\] 3 REG LC_X17_Y22_N9 6 " "Info: 3: + IC(2.462 ns) + CELL(0.867 ns) = 15.599 ns; Loc. = LC_X17_Y22_N9; Fanout = 6; REG Node = 'jiao_tong:inst\|qh\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[0] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 17.81 % ) " "Info: Total cell delay = 2.778 ns ( 17.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.821 ns ( 82.19 % ) " "Info: Total interconnect delay = 12.821 ns ( 82.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.599 ns" { jin jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.599 ns" { jin {} jin~out0 {} jiao_tong:inst|qh[3]~780 {} jiao_tong:inst|qh[0] {} } { 0.000ns 0.000ns 10.359ns 2.462ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst1\|altpll:altpll_component\|_clk0 -2.054 ns - " "Info: - Offset between input clock \"clk\" and output clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 80 40 208 96 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.974 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|qh\[0\] 4 REG LC_X17_Y22_N9 6 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y22_N9; Fanout = 6; REG Node = 'jiao_tong:inst\|qh\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|qh[0] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[0] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.599 ns" { jin jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.599 ns" { jin {} jin~out0 {} jiao_tong:inst|qh[3]~780 {} jiao_tong:inst|qh[0] {} } { 0.000ns 0.000ns 10.359ns 2.462ns } { 0.000ns 1.469ns 0.442ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[0] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[4\] jiao_tong:inst\|ql\[3\] 23.150 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[4\]\" through register \"jiao_tong:inst\|ql\[3\]\" is 23.150 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 80 40 208 96 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 11.974 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|ql\[3\] 4 REG LC_X17_Y23_N5 4 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y23_N5; Fanout = 4; REG Node = 'jiao_tong:inst\|ql\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|ql[3] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|ql[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|ql[3] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.006 ns + Longest register pin " "Info: + Longest register to pin delay is 13.006 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|ql\[3\] 1 REG LC_X17_Y23_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y23_N5; Fanout = 4; REG Node = 'jiao_tong:inst\|ql\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|ql[3] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.671 ns) + CELL(0.292 ns) 1.963 ns jiao_tong:inst\|Mux0~14 2 COMB LC_X18_Y22_N2 7 " "Info: 2: + IC(1.671 ns) + CELL(0.292 ns) = 1.963 ns; Loc. = LC_X18_Y22_N2; Fanout = 7; COMB Node = 'jiao_tong:inst\|Mux0~14'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.963 ns" { jiao_tong:inst|ql[3] jiao_tong:inst|Mux0~14 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 190 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.178 ns) + CELL(0.442 ns) 5.583 ns jiao_tong:inst\|Mux9~24 3 COMB LC_X38_Y19_N8 1 " "Info: 3: + IC(3.178 ns) + CELL(0.442 ns) = 5.583 ns; Loc. = LC_X38_Y19_N8; Fanout = 1; COMB Node = 'jiao_tong:inst\|Mux9~24'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.620 ns" { jiao_tong:inst|Mux0~14 jiao_tong:inst|Mux9~24 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 199 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.442 ns) 7.203 ns jiao_tong:inst\|seg7\[4\]~67 4 COMB LC_X38_Y18_N5 1 " "Info: 4: + IC(1.178 ns) + CELL(0.442 ns) = 7.203 ns; Loc. = LC_X38_Y18_N5; Fanout = 1; COMB Node = 'jiao_tong:inst\|seg7\[4\]~67'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.620 ns" { jiao_tong:inst|Mux9~24 jiao_tong:inst|seg7[4]~67 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.679 ns) + CELL(2.124 ns) 13.006 ns seg7\[4\] 5 PIN PIN_140 0 " "Info: 5: + IC(3.679 ns) + CELL(2.124 ns) = 13.006 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'seg7\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.803 ns" { jiao_tong:inst|seg7[4]~67 seg7[4] } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 432 608 280 "seg7\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns ( 25.37 % ) " "Info: Total cell delay = 3.300 ns ( 25.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.706 ns ( 74.63 % ) " "Info: Total interconnect delay = 9.706 ns ( 74.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.006 ns" { jiao_tong:inst|ql[3] jiao_tong:inst|Mux0~14 jiao_tong:inst|Mux9~24 jiao_tong:inst|seg7[4]~67 seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.006 ns" { jiao_tong:inst|ql[3] {} jiao_tong:inst|Mux0~14 {} jiao_tong:inst|Mux9~24 {} jiao_tong:inst|seg7[4]~67 {} seg7[4] {} } { 0.000ns 1.671ns 3.178ns 1.178ns 3.679ns } { 0.000ns 0.292ns 0.442ns 0.442ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|ql[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|ql[3] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.006 ns" { jiao_tong:inst|ql[3] jiao_tong:inst|Mux0~14 jiao_tong:inst|Mux9~24 jiao_tong:inst|seg7[4]~67 seg7[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.006 ns" { jiao_tong:inst|ql[3] {} jiao_tong:inst|Mux0~14 {} jiao_tong:inst|Mux9~24 {} jiao_tong:inst|seg7[4]~67 {} seg7[4] {} } { 0.000ns 1.671ns 3.178ns 1.178ns 3.679ns } { 0.000ns 0.292ns 0.442ns 0.442ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "jin yb 20.012 ns Longest " "Info: Longest tpd from source pin \"jin\" to destination pin \"yb\" is 20.012 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns jin 1 PIN PIN_122 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 22; PIN Node = 'jin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jin } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 264 112 280 280 "jin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(11.288 ns) + CELL(0.292 ns) 13.049 ns jiao_tong:inst\|yb~4 2 COMB LC_X16_Y22_N1 1 " "Info: 2: + IC(11.288 ns) + CELL(0.292 ns) = 13.049 ns; Loc. = LC_X16_Y22_N1; Fanout = 1; COMB Node = 'jiao_tong:inst\|yb~4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.580 ns" { jin jiao_tong:inst|yb~4 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.839 ns) + CELL(2.124 ns) 20.012 ns yb 3 PIN PIN_49 0 " "Info: 3: + IC(4.839 ns) + CELL(2.124 ns) = 20.012 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'yb'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.963 ns" { jiao_tong:inst|yb~4 yb } "NODE_NAME" } } { "jiao_tong_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong_test.bdf" { { 344 432 608 360 "yb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.885 ns ( 19.41 % ) " "Info: Total cell delay = 3.885 ns ( 19.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.127 ns ( 80.59 % ) " "Info: Total interconnect delay = 16.127 ns ( 80.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "20.012 ns" { jin jiao_tong:inst|yb~4 yb } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "20.012 ns" { jin {} jin~out0 {} jiao_tong:inst|yb~4 {} yb {} } { 0.000ns 0.000ns 11.288ns 4.839ns } { 0.000ns 1.469ns 0.292ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}