prev_cmp_jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register jiao_tong:inst\|qh\[1\] register jiao_tong:inst\|qh\[2\] 41.894 ns " "Info: Slack time is 41.894 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"jiao_tong:inst\|qh\[1\]\" and destination register \"jiao_tong:inst\|qh\[2\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "123.37 MHz 8.106 ns " "Info: Fmax is 123.37 MHz (period= 8.106 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.739 ns + Largest register register " "Info: + Largest register to register requirement is 49.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 47.946 ns " "Info: + Latch edge is 47.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.974 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|qh\[2\] 4 REG LC_X17_Y22_N3 4 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y22_N3; Fanout = 4; REG Node = 'jiao_tong:inst\|qh\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|qh[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[2] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 11.974 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|qh\[1\] 4 REG LC_X17_Y22_N6 5 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y22_N6; Fanout = 5; REG Node = 'jiao_tong:inst\|qh\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[1] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[2] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[1] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[2] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[1] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.845 ns - Longest register register " "Info: - Longest register to register delay is 7.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|qh\[1\] 1 REG LC_X17_Y22_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y22_N6; Fanout = 5; REG Node = 'jiao_tong:inst\|qh\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|qh[1] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.077 ns) + CELL(0.292 ns) 2.369 ns jiao_tong:inst\|process2~14 2 COMB LC_X17_Y22_N5 2 " "Info: 2: + IC(2.077 ns) + CELL(0.292 ns) = 2.369 ns; Loc. = LC_X17_Y22_N5; Fanout = 2; COMB Node = 'jiao_tong:inst\|process2~14'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.369 ns" { jiao_tong:inst|qh[1] jiao_tong:inst|process2~14 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.114 ns) 2.920 ns jiao_tong:inst\|qh\[3\]~775 3 COMB LC_X17_Y22_N8 3 " "Info: 3: + IC(0.437 ns) + CELL(0.114 ns) = 2.920 ns; Loc. = LC_X17_Y22_N8; Fanout = 3; COMB Node = 'jiao_tong:inst\|qh\[3\]~775'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.551 ns" { jiao_tong:inst|process2~14 jiao_tong:inst|qh[3]~775 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.114 ns) 3.786 ns jiao_tong:inst\|ql\[0\]~419 4 COMB LC_X17_Y22_N7 1 " "Info: 4: + IC(0.752 ns) + CELL(0.114 ns) = 3.786 ns; Loc. = LC_X17_Y22_N7; Fanout = 1; COMB Node = 'jiao_tong:inst\|ql\[0\]~419'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.866 ns" { jiao_tong:inst|qh[3]~775 jiao_tong:inst|ql[0]~419 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 4.516 ns jiao_tong:inst\|qh\[3\]~780 5 COMB LC_X17_Y22_N2 4 " "Info: 5: + IC(0.438 ns) + CELL(0.292 ns) = 4.516 ns; Loc. = LC_X17_Y22_N2; Fanout = 4; COMB Node = 'jiao_tong:inst\|qh\[3\]~780'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { jiao_tong:inst|ql[0]~419 jiao_tong:inst|qh[3]~780 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.462 ns) + CELL(0.867 ns) 7.845 ns jiao_tong:inst\|qh\[2\] 6 REG LC_X17_Y22_N3 4 " "Info: 6: + IC(2.462 ns) + CELL(0.867 ns) = 7.845 ns; Loc. = LC_X17_Y22_N3; Fanout = 4; REG Node = 'jiao_tong:inst\|qh\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.329 ns" { jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[2] } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.679 ns ( 21.40 % ) " "Info: Total cell delay = 1.679 ns ( 21.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.166 ns ( 78.60 % ) " "Info: Total interconnect delay = 6.166 ns ( 78.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.845 ns" { jiao_tong:inst|qh[1] jiao_tong:inst|process2~14 jiao_tong:inst|qh[3]~775 jiao_tong:inst|ql[0]~419 jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.845 ns" { jiao_tong:inst|qh[1] {} jiao_tong:inst|process2~14 {} jiao_tong:inst|qh[3]~775 {} jiao_tong:inst|ql[0]~419 {} jiao_tong:inst|qh[3]~780 {} jiao_tong:inst|qh[2] {} } { 0.000ns 2.077ns 0.437ns 0.752ns 0.438ns 2.462ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[2] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|qh[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|qh[1] {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.845 ns" { jiao_tong:inst|qh[1] jiao_tong:inst|process2~14 jiao_tong:inst|qh[3]~775 jiao_tong:inst|ql[0]~419 jiao_tong:inst|qh[3]~780 jiao_tong:inst|qh[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.845 ns" { jiao_tong:inst|qh[1] {} jiao_tong:inst|process2~14 {} jiao_tong:inst|qh[3]~775 {} jiao_tong:inst|ql[0]~419 {} jiao_tong:inst|qh[3]~780 {} jiao_tong:inst|qh[2] {} } { 0.000ns 2.077ns 0.437ns 0.752ns 0.438ns 2.462ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register jiao_tong:inst\|stx.st3 register jiao_tong:inst\|stx.st4 876 ps " "Info: Minimum slack time is 876 ps for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"jiao_tong:inst\|stx.st3\" and destination register \"jiao_tong:inst\|stx.st4\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.667 ns + Shortest register register " "Info: + Shortest register to register delay is 0.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jiao_tong:inst\|stx.st3 1 REG LC_X17_Y22_N8 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y22_N8; Fanout = 7; REG Node = 'jiao_tong:inst\|stx.st3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.115 ns) 0.667 ns jiao_tong:inst\|stx.st4 2 REG LC_X17_Y22_N1 6 " "Info: 2: + IC(0.552 ns) + CELL(0.115 ns) = 0.667 ns; Loc. = LC_X17_Y22_N1; Fanout = 6; REG Node = 'jiao_tong:inst\|stx.st4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.667 ns" { jiao_tong:inst|stx.st3 jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.24 % ) " "Info: Total cell delay = 0.115 ns ( 17.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.552 ns ( 82.76 % ) " "Info: Total interconnect delay = 0.552 ns ( 82.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.667 ns" { jiao_tong:inst|stx.st3 jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.667 ns" { jiao_tong:inst|stx.st3 {} jiao_tong:inst|stx.st4 {} } { 0.000ns 0.552ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 11.974 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|stx.st4 4 REG LC_X17_Y22_N1 6 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y22_N1; Fanout = 6; REG Node = 'jiao_tong:inst\|stx.st4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st4 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 11.974 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 11.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns jiao_tong:inst\|clk1khz 2 REG LC_X8_Y13_N6 11 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 11; REG Node = 'jiao_tong:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.935 ns) 7.256 ns jiao_tong:inst\|clk1hz 3 REG LC_X9_Y13_N8 26 " "Info: 3: + IC(3.608 ns) + CELL(0.935 ns) = 7.256 ns; Loc. = LC_X9_Y13_N8; Fanout = 26; REG Node = 'jiao_tong:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.543 ns" { jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.007 ns) + CELL(0.711 ns) 11.974 ns jiao_tong:inst\|stx.st3 4 REG LC_X17_Y22_N8 7 " "Info: 4: + IC(4.007 ns) + CELL(0.711 ns) = 11.974 ns; Loc. = LC_X17_Y22_N8; Fanout = 7; REG Node = 'jiao_tong:inst\|stx.st3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.718 ns" { jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.56 % ) " "Info: Total cell delay = 2.581 ns ( 21.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 78.44 % ) " "Info: Total interconnect delay = 9.393 ns ( 78.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st4 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st4 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.667 ns" { jiao_tong:inst|stx.st3 jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.667 ns" { jiao_tong:inst|stx.st3 {} jiao_tong:inst|stx.st4 {} } { 0.000ns 0.552ns } { 0.000ns 0.115ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st4 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 jiao_tong:inst|clk1khz jiao_tong:inst|clk1hz jiao_tong:inst|stx.st3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.974 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} jiao_tong:inst|clk1khz {} jiao_tong:inst|clk1hz {} jiao_tong:inst|stx.st3 {} } { 0.000ns 1.778ns 3.608ns 4.007ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}