prev_cmp_jiao_tong.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "jiao_tong:inst\|clk1hz " "Info: Detected ripple clock \"jiao_tong:inst\|clk1hz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jiao_tong:inst\|clk1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jiao_tong:inst\|clk1khz " "Info: Detected ripple clock \"jiao_tong:inst\|clk1khz\" as buffer" {  } { { "jiao_tong.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/jiao_tong/jiao_tong.vhd" 15 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "jiao_tong:inst\|clk1khz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}