jiao_tong.hier_info

FPGA和VHDL的全过程和源码

|jiao_tong_test
ra <= jiao_tong:inst.ra
clk => altpll0:inst1.inclk0
jin => jiao_tong:inst.jin
ya <= jiao_tong:inst.ya
ga <= jiao_tong:inst.ga
rb <= jiao_tong:inst.rb
yb <= jiao_tong:inst.yb
gb <= jiao_tong:inst.gb
scan[0] <= jiao_tong:inst.scan[0]
scan[1] <= jiao_tong:inst.scan[1]
seg7[0] <= jiao_tong:inst.seg7[0]
seg7[1] <= jiao_tong:inst.seg7[1]
seg7[2] <= jiao_tong:inst.seg7[2]
seg7[3] <= jiao_tong:inst.seg7[3]
seg7[4] <= jiao_tong:inst.seg7[4]
seg7[5] <= jiao_tong:inst.seg7[5]
seg7[6] <= jiao_tong:inst.seg7[6]


|jiao_tong_test|jiao_tong:inst
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => clk1khz.CLK
jin => rb~0.IN1
jin => ra~0.IN1
jin => stx~32.OUTPUTSELECT
jin => y2~3.OUTPUTSELECT
jin => stx~29.OUTPUTSELECT
jin => stx~28.OUTPUTSELECT
jin => g2~3.OUTPUTSELECT
jin => r2~3.OUTPUTSELECT
jin => r1~3.OUTPUTSELECT
jin => ql~43.OUTPUTSELECT
jin => ql~42.OUTPUTSELECT
jin => ql~41.OUTPUTSELECT
jin => ql~40.OUTPUTSELECT
jin => qh~43.OUTPUTSELECT
jin => qh~42.OUTPUTSELECT
jin => qh~41.OUTPUTSELECT
jin => qh~40.OUTPUTSELECT
jin => stx~23.OUTPUTSELECT
jin => stx~22.OUTPUTSELECT
jin => stx~21.OUTPUTSELECT
jin => stx~20.OUTPUTSELECT
jin => g1~3.OUTPUTSELECT
jin => y1~3.OUTPUTSELECT
jin => a~5.OUTPUTSELECT
jin => ql~27.OUTPUTSELECT
jin => ql~26.OUTPUTSELECT
jin => ql~25.OUTPUTSELECT
jin => ql~24.OUTPUTSELECT
jin => qh~27.OUTPUTSELECT
jin => qh~26.OUTPUTSELECT
jin => qh~25.OUTPUTSELECT
jin => qh~24.OUTPUTSELECT
jin => stx~11.OUTPUTSELECT
jin => stx~10.OUTPUTSELECT
jin => stx~9.OUTPUTSELECT
jin => stx~8.OUTPUTSELECT
jin => g2~1.OUTPUTSELECT
jin => y2~1.OUTPUTSELECT
jin => r2~1.OUTPUTSELECT
jin => g1~1.OUTPUTSELECT
jin => y1~1.OUTPUTSELECT
jin => r1~1.OUTPUTSELECT
jin => a~2.OUTPUTSELECT
jin => ql~15.OUTPUTSELECT
jin => ql~14.OUTPUTSELECT
jin => ql~13.OUTPUTSELECT
jin => ql~12.OUTPUTSELECT
jin => qh~15.OUTPUTSELECT
jin => qh~14.OUTPUTSELECT
jin => qh~13.OUTPUTSELECT
jin => qh~12.OUTPUTSELECT
jin => gb~0.IN1
jin => yb~0.IN1
jin => ga~0.IN1
jin => ya~0.IN1
jin => seg7~13.OUTPUTSELECT
jin => seg7~12.OUTPUTSELECT
jin => seg7~11.OUTPUTSELECT
jin => seg7~10.OUTPUTSELECT
jin => seg7~9.OUTPUTSELECT
jin => seg7~8.OUTPUTSELECT
jin => seg7~7.OUTPUTSELECT
jin => yb~1.OUTPUTSELECT
jin => ya~1.OUTPUTSELECT
jin => gb~1.OUTPUTSELECT
jin => ga~1.OUTPUTSELECT
jin => rb~1.OUTPUTSELECT
jin => ra~1.OUTPUTSELECT
scan[0] <= scan[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
scan[1] <= scan[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
seg7[0] <= seg7~13.DB_MAX_OUTPUT_PORT_TYPE
seg7[1] <= seg7~12.DB_MAX_OUTPUT_PORT_TYPE
seg7[2] <= seg7~11.DB_MAX_OUTPUT_PORT_TYPE
seg7[3] <= seg7~10.DB_MAX_OUTPUT_PORT_TYPE
seg7[4] <= seg7~9.DB_MAX_OUTPUT_PORT_TYPE
seg7[5] <= seg7~8.DB_MAX_OUTPUT_PORT_TYPE
seg7[6] <= seg7~7.DB_MAX_OUTPUT_PORT_TYPE
ra <= ra~1.DB_MAX_OUTPUT_PORT_TYPE
ya <= ya~1.DB_MAX_OUTPUT_PORT_TYPE
ga <= ga~1.DB_MAX_OUTPUT_PORT_TYPE
rb <= rb~1.DB_MAX_OUTPUT_PORT_TYPE
yb <= yb~1.DB_MAX_OUTPUT_PORT_TYPE
gb <= gb~1.DB_MAX_OUTPUT_PORT_TYPE


|jiao_tong_test|altpll0:inst1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|jiao_tong_test|altpll0:inst1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>