📄 jiao_tong.map.rpt
字号:
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 6 ; Untyped ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sun Apr 27 07:24:23 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiao_tong -c jiao_tong
Info: Found 2 design units, including 1 entities, in source file altpll0.vhd
Info: Found design unit 1: altpll0-SYN
Info: Found entity 1: altpll0
Info: Found 2 design units, including 1 entities, in source file jiao_tong.vhd
Info: Found design unit 1: jiao_tong-onejt
Info: Found entity 1: jiao_tong
Info: Found 1 design units, including 1 entities, in source file jiao_tong_test.bdf
Info: Found entity 1: jiao_tong_test
Info: Elaborating entity "jiao_tong_test" for the top level hierarchy
Info: Elaborating entity "jiao_tong" for hierarchy "jiao_tong:inst"
Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(188): inferring latch(es) for signal or variable "data", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at jiao_tong.vhd(188): inferring latch(es) for signal or variable "scan", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "scan[0]" at jiao_tong.vhd(188)
Info (10041): Inferred latch for "scan[1]" at jiao_tong.vhd(188)
Info (10041): Inferred latch for "data[0]" at jiao_tong.vhd(188)
Info (10041): Inferred latch for "data[1]" at jiao_tong.vhd(188)
Info (10041): Inferred latch for "data[2]" at jiao_tong.vhd(188)
Info (10041): Inferred latch for "data[3]" at jiao_tong.vhd(188)
Info: Elaborating entity "altpll0" for hierarchy "altpll0:inst1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "altpll0:inst1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "altpll0:inst1|altpll:altpll_component"
Info: Duplicate registers merged to single register
Info: Duplicate register "jiao_tong:inst|r2" merged to single register "jiao_tong:inst|r1", power-up level changed
Info: State machine "|jiao_tong_test|jiao_tong:inst|stx" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|jiao_tong_test|jiao_tong:inst|stx"
Info: Encoding result for state machine "|jiao_tong_test|jiao_tong:inst|stx"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "jiao_tong:inst|stx.st4"
Info: Encoded state bit "jiao_tong:inst|stx.st3"
Info: Encoded state bit "jiao_tong:inst|stx.st2"
Info: Encoded state bit "jiao_tong:inst|stx.st1"
Info: State "|jiao_tong_test|jiao_tong:inst|stx.st1" uses code string "0000"
Info: State "|jiao_tong_test|jiao_tong:inst|stx.st2" uses code string "0011"
Info: State "|jiao_tong_test|jiao_tong:inst|stx.st3" uses code string "0101"
Info: State "|jiao_tong_test|jiao_tong:inst|stx.st4" uses code string "1001"
Info: Duplicate registers merged to single register
Info: Duplicate register "jiao_tong:inst|\process2:count[0]" merged to single register "jiao_tong:inst|cnt[0]"
Warning (14130): Reduced register "jiao_tong:inst|cnt[1]" with stuck data_in port to stuck value GND
Warning: LATCH primitive "jiao_tong:inst|scan[1]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst|scan[0]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst|data[0]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst|data[1]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst|data[2]" is permanently enabled
Warning: LATCH primitive "jiao_tong:inst|data[3]" is permanently enabled
Info: Implemented 134 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 15 output pins
Info: Implemented 116 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
Info: Allocated 163 megabytes of memory during processing
Info: Processing ended: Sun Apr 27 07:24:29 2008
Info: Elapsed time: 00:00:06
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