jiao_tong.cdf

来自「FPGA和VHDL的全过程和源码」· CDF 代码 · 共 14 行

/* Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Cfg)
		Device PartName(EP1C12Q240) Path("D:/lecture/embed/FPGA/FPGAExample/jiao_tong/") File("jiao_tong.sof") MfrSpec(OpMask(1));

ChainEnd;

AlteraBegin;
	ChainType(JTAG);
AlteraEnd;