jiao_tong.tan.summary

FPGA和VHDL的全过程和源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.885 ns
From           : jin
To             : jiao_tong:inst|stx.st3
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.306 ns
From           : jiao_tong:inst|ql[1]
To             : seg7[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 16.767 ns
From           : jin
To             : ra
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.422 ns
From           : jin
To             : jiao_tong:inst|ql[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 42.764 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : 138.20 MHz ( period = 7.236 ns )
From           : jiao_tong:inst|cnt[0]
To             : jiao_tong:inst|\process2:count[6]
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst1|altpll:altpll_component|_clk0'
Slack          : 1.039 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : jiao_tong:inst|a
To             : jiao_tong:inst|a
From Clock     : altpll0:inst1|altpll:altpll_component|_clk0
To Clock       : altpll0:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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