clock_6.tan.summary

FPGA和VHDL的全过程和源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.694 ns
From           : en
To             : clock_6:inst|min[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 27.161 ns
From           : clock_6:inst|sec[3]
To             : seg7[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.517 ns
From           : inc
To             : clock_6:inst|inc_reg
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst2|altpll:altpll_component|_clk0'
Slack          : 42.611 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : 135.34 MHz ( period = 7.389 ns )
From           : clock_6:inst|cnt[0]
To             : clock_6:inst|\process3:count[5]
From Clock     : altpll0:inst2|altpll:altpll_component|_clk0
To Clock       : altpll0:inst2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'mode'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : clock_6:inst|state[1]
To             : clock_6:inst|state[1]
From Clock     : mode
To Clock       : mode
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst2|altpll:altpll_component|_clk0'
Slack          : 1.104 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : clock_6:inst|min[4]
To             : clock_6:inst|min[4]
From Clock     : altpll0:inst2|altpll:altpll_component|_clk0
To Clock       : altpll0:inst2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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