📄 prev_cmp_clock_6.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 22 12:05:22 2008 " "Info: Processing started: Tue Apr 22 12:05:22 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off clock_6 -c clock_6 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off clock_6 -c clock_6" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 22 12:05:26 2008 " "Info: Processing ended: Tue Apr 22 12:05:26 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 22 12:05:27 2008 " "Info: Processing started: Tue Apr 22 12:05:27 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock_6 -c clock_6 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock_6 -c clock_6 --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mode " "Info: Assuming node \"mode\" is an undefined clock" { } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_6:inst\|clk1khz " "Info: Detected ripple clock \"clock_6:inst\|clk1khz\" as buffer" { } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock_6:inst\|clk1khz" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clock_6:inst\|clk1hz " "Info: Detected ripple clock \"clock_6:inst\|clk1hz\" as buffer" { } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock_6:inst\|clk1hz" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 register clock_6:inst\|cnt\[0\] register clock_6:inst\|\\process3:count\[5\] 42.972 ns " "Info: Slack time is 42.972 ns for clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" between source register \"clock_6:inst\|cnt\[0\]\" and destination register \"clock_6:inst\|\\process3:count\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "142.29 MHz 7.028 ns " "Info: Fmax is 142.29 MHz (period= 7.028 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.750 ns + Largest register register " "Info: + Largest register to register requirement is 49.750 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 47.946 ns " "Info: + Latch edge is 47.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns 50 " "Info: Clock period of Destination clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with offset of -2.054 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns 50 " "Info: Clock period of Source clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with offset of -2.054 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.011 ns + Largest " "Info: + Largest clock skew is 0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 destination 7.014 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to destination register is 7.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X8_Y13_N6 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.590 ns) + CELL(0.711 ns) 7.014 ns clock_6:inst\|\\process3:count\[5\] 3 REG LC_X30_Y17_N7 4 " "Info: 3: + IC(3.590 ns) + CELL(0.711 ns) = 7.014 ns; Loc. = LC_X30_Y17_N7; Fanout = 4; REG Node = 'clock_6:inst\|\\process3:count\[5\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.301 ns" { clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.47 % ) " "Info: Total cell delay = 1.646 ns ( 23.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.368 ns ( 76.53 % ) " "Info: Total interconnect delay = 5.368 ns ( 76.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.590ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 source 7.003 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to source register is 7.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X8_Y13_N6 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.579 ns) + CELL(0.711 ns) 7.003 ns clock_6:inst\|cnt\[0\] 3 REG LC_X7_Y10_N4 23 " "Info: 3: + IC(3.579 ns) + CELL(0.711 ns) = 7.003 ns; Loc. = LC_X7_Y10_N4; Fanout = 23; REG Node = 'clock_6:inst\|cnt\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.290 ns" { clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 23.50 % ) " "Info: Total cell delay = 1.646 ns ( 23.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.357 ns ( 76.50 % ) " "Info: Total interconnect delay = 5.357 ns ( 76.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.579ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.590ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.579ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.590ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.579ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.778 ns - Longest register register " "Info: - Longest register to register delay is 6.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_6:inst\|cnt\[0\] 1 REG LC_X7_Y10_N4 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y10_N4; Fanout = 23; REG Node = 'clock_6:inst\|cnt\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|cnt[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.735 ns) + CELL(0.564 ns) 4.299 ns clock_6:inst\|Add2~122 2 COMB LC_X30_Y16_N1 2 " "Info: 2: + IC(3.735 ns) + CELL(0.564 ns) = 4.299 ns; Loc. = LC_X30_Y16_N1; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~122'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.299 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.377 ns clock_6:inst\|Add2~124 3 COMB LC_X30_Y16_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 4.377 ns; Loc. = LC_X30_Y16_N2; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~124'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { clock_6:inst|Add2~122 clock_6:inst|Add2~124 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.455 ns clock_6:inst\|Add2~120 4 COMB LC_X30_Y16_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 4.455 ns; Loc. = LC_X30_Y16_N3; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~120'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { clock_6:inst|Add2~124 clock_6:inst|Add2~120 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 4.633 ns clock_6:inst\|Add2~126 5 COMB LC_X30_Y16_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 4.633 ns; Loc. = LC_X30_Y16_N4; Fanout = 3; COMB Node = 'clock_6:inst\|Add2~126'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { clock_6:inst|Add2~120 clock_6:inst|Add2~126 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 5.254 ns clock_6:inst\|Add2~127 6 COMB LC_X30_Y16_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 5.254 ns; Loc. = LC_X30_Y16_N5; Fanout = 1; COMB Node = 'clock_6:inst\|Add2~127'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { clock_6:inst|Add2~126 clock_6:inst|Add2~127 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.309 ns) 6.778 ns clock_6:inst\|\\process3:count\[5\] 7 REG LC_X30_Y17_N7 4 " "Info: 7: + IC(1.215 ns) + CELL(0.309 ns) = 6.778 ns; Loc. = LC_X30_Y17_N7; Fanout = 4; REG Node = 'clock_6:inst\|\\process3:count\[5\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.828 ns ( 26.97 % ) " "Info: Total cell delay = 1.828 ns ( 26.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.950 ns ( 73.03 % ) " "Info: Total interconnect delay = 4.950 ns ( 73.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.778 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 clock_6:inst|Add2~124 clock_6:inst|Add2~120 clock_6:inst|Add2~126 clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.778 ns" { clock_6:inst|cnt[0] {} clock_6:inst|Add2~122 {} clock_6:inst|Add2~124 {} clock_6:inst|Add2~120 {} clock_6:inst|Add2~126 {} clock_6:inst|Add2~127 {} clock_6:inst|\process3:count[5] {} } { 0.000ns 3.735ns 0.000ns 0.000ns 0.000ns 0.000ns 1.215ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.014 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.590ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.003 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.579ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.778 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 clock_6:inst|Add2~124 clock_6:inst|Add2~120 clock_6:inst|Add2~126 clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.778 ns" { clock_6:inst|cnt[0] {} clock_6:inst|Add2~122 {} clock_6:inst|Add2~124 {} clock_6:inst|Add2~120 {} clock_6:inst|Add2~126 {} clock_6:inst|Add2~127 {} clock_6:inst|\process3:count[5] {} } { 0.000ns 3.735ns 0.000ns 0.000ns 0.000ns 0.000ns 1.215ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.309ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register clock_6:inst\|state\[0\] clock_6:inst\|state\[1\] 275.03 MHz Internal " "Info: Clock \"mode\" Internal fmax is restricted to 275.03 MHz between source register \"clock_6:inst\|state\[0\]\" and destination register \"clock_6:inst\|state\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.437 ns + Longest register register " "Info: + Longest register to register delay is 1.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_6:inst\|state\[0\] 1 REG LC_X30_Y18_N9 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y18_N9; Fanout = 14; REG Node = 'clock_6:inst\|state\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|state[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.738 ns) 1.437 ns clock_6:inst\|state\[1\] 2 REG LC_X30_Y18_N2 13 " "Info: 2: + IC(0.699 ns) + CELL(0.738 ns) = 1.437 ns; Loc. = LC_X30_Y18_N2; Fanout = 13; REG Node = 'clock_6:inst\|state\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clock_6:inst|state[0] clock_6:inst|state[1] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 51.36 % ) " "Info: Total cell delay = 0.738 ns ( 51.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.699 ns ( 48.64 % ) " "Info: Total interconnect delay = 0.699 ns ( 48.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clock_6:inst|state[0] clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.437 ns" { clock_6:inst|state[0] {} clock_6:inst|state[1] {} } { 0.000ns 0.699ns } { 0.000ns 0.738ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 8.141 ns + Shortest register " "Info: + Shortest clock path from clock \"mode\" to destination register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mode 1 CLK PIN_121 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 2; CLK Node = 'mode'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.961 ns) + CELL(0.711 ns) 8.141 ns clock_6:inst\|state\[1\] 2 REG LC_X30_Y18_N2 13 " "Info: 2: + IC(5.961 ns) + CELL(0.711 ns) = 8.141 ns; Loc. = LC_X30_Y18_N2; Fanout = 13; REG Node = 'clock_6:inst\|state\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.78 % ) " "Info: Total cell delay = 2.180 ns ( 26.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.961 ns ( 73.22 % ) " "Info: Total interconnect delay = 5.961 ns ( 73.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[1] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 8.141 ns - Longest register " "Info: - Longest clock path from clock \"mode\" to source register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mode 1 CLK PIN_121 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 2; CLK Node = 'mode'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.961 ns) + CELL(0.711 ns) 8.141 ns clock_6:inst\|state\[0\] 2 REG LC_X30_Y18_N9 14 " "Info: 2: + IC(5.961 ns) + CELL(0.711 ns) = 8.141 ns; Loc. = LC_X30_Y18_N9; Fanout = 14; REG Node = 'clock_6:inst\|state\[0\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.78 % ) " "Info: Total cell delay = 2.180 ns ( 26.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.961 ns ( 73.22 % ) " "Info: Total interconnect delay = 5.961 ns ( 73.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[0] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[1] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[0] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s⌨️ 快捷键说明
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