prev_cmp_clock_6.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock_6:inst\|clk1khz Global clock " "Info: Automatically promoted some destinations of signal \"clock_6:inst\|clk1khz\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_6:inst\|clk1khz " "Info: Destination \"clock_6:inst\|clk1khz\" may be non-global or may not use global clock" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock_6:inst\|clk1hz Global clock " "Info: Automatically promoted some destinations of signal \"clock_6:inst\|clk1hz\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_6:inst\|clk1hz " "Info: Destination \"clock_6:inst\|clk1hz\" may be non-global or may not use global clock" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "mode Global clock " "Info: Automatically promoted signal \"mode\" to use Global clock" {  } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "mode " "Info: Pin \"mode\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { mode } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock_6:inst\|hour\[4\]~0 Global clock " "Info: Automatically promoted signal \"clock_6:inst\|hour\[4\]~0\" to use Global clock" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clr Global clock " "Info: Automatically promoted some destinations of signal \"clr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_6:inst\|hour\[4\]~0 " "Info: Destination \"clock_6:inst\|hour\[4\]~0\" may be non-global or may not use global clock" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_6:inst\|inc_reg~128 " "Info: Destination \"clock_6:inst\|inc_reg~128\" may be non-global or may not use global clock" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 20 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 200 88 256 216 "clr" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clr " "Info: Pin \"clr\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { clr } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clr" } } } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 200 88 256 216 "clr" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "seg7\[7\] " "Warning: Node \"seg7\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg7\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}