clock_6.hier_info

FPGA和VHDL的全过程和源码

|clock_6_test
scan[0] <= clock_6:inst.scan[0]
scan[1] <= clock_6:inst.scan[1]
scan[2] <= clock_6:inst.scan[2]
scan[3] <= clock_6:inst.scan[3]
scan[4] <= clock_6:inst.scan[4]
scan[5] <= clock_6:inst.scan[5]
clk => altpll0:inst2.inclk0
clr => clock_6:inst.clr
en => clock_6:inst.en
mode => clock_6:inst.mode
inc => clock_6:inst.inc
seg7[0] <= clock_6:inst.seg7[0]
seg7[1] <= clock_6:inst.seg7[1]
seg7[2] <= clock_6:inst.seg7[2]
seg7[3] <= clock_6:inst.seg7[3]
seg7[4] <= clock_6:inst.seg7[4]
seg7[5] <= clock_6:inst.seg7[5]
seg7[6] <= clock_6:inst.seg7[6]


|clock_6_test|clock_6:inst
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => clk1khz.CLK
clr => state[0].ACLR
clr => state[1].ACLR
clr => hour[4]~0.IN0
clr => inc_reg~0.OUTPUTSELECT
en => hour[4]~0.IN1
en => hour[4].ENA
en => hour[3].ENA
en => hour[2].ENA
en => hour[1].ENA
en => hour[0].ENA
en => min[5].ENA
en => min[4].ENA
en => min[3].ENA
en => min[2].ENA
en => min[1].ENA
en => min[0].ENA
en => sec[5].ENA
en => sec[4].ENA
en => sec[3].ENA
en => sec[2].ENA
en => sec[1].ENA
en => sec[0].ENA
en => inc_reg.ENA
mode => state[1].CLK
mode => state[0].CLK
inc => sec~12.OUTPUTSELECT
inc => sec~13.OUTPUTSELECT
inc => sec~14.OUTPUTSELECT
inc => sec~15.OUTPUTSELECT
inc => sec~16.OUTPUTSELECT
inc => sec~17.OUTPUTSELECT
inc => min~18.OUTPUTSELECT
inc => min~19.OUTPUTSELECT
inc => min~20.OUTPUTSELECT
inc => min~21.OUTPUTSELECT
inc => min~22.OUTPUTSELECT
inc => min~23.OUTPUTSELECT
inc => hour~25.OUTPUTSELECT
inc => hour~24.OUTPUTSELECT
inc => hour~23.OUTPUTSELECT
inc => hour~22.OUTPUTSELECT
inc => hour~21.OUTPUTSELECT
inc => Mux17.IN0
inc => Mux17.IN1
inc => Mux17.IN2
seg7[0] <= Mux54.DB_MAX_OUTPUT_PORT_TYPE
seg7[1] <= Mux53.DB_MAX_OUTPUT_PORT_TYPE
seg7[2] <= Mux52.DB_MAX_OUTPUT_PORT_TYPE
seg7[3] <= Mux51.DB_MAX_OUTPUT_PORT_TYPE
seg7[4] <= Mux50.DB_MAX_OUTPUT_PORT_TYPE
seg7[5] <= Mux49.DB_MAX_OUTPUT_PORT_TYPE
seg7[6] <= Mux48.DB_MAX_OUTPUT_PORT_TYPE
scan[0] <= Mux47.DB_MAX_OUTPUT_PORT_TYPE
scan[1] <= Mux46.DB_MAX_OUTPUT_PORT_TYPE
scan[2] <= Mux45.DB_MAX_OUTPUT_PORT_TYPE
scan[3] <= Mux44.DB_MAX_OUTPUT_PORT_TYPE
scan[4] <= Mux43.DB_MAX_OUTPUT_PORT_TYPE
scan[5] <= Mux42.DB_MAX_OUTPUT_PORT_TYPE


|clock_6_test|altpll0:inst2
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|clock_6_test|altpll0:inst2|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>