clock_6.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[6\] clock_6:inst\|sec\[3\] 27.161 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[6\]\" through register \"clock_6:inst\|sec\[3\]\" is 27.161 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst2\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"clk\" and output clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 24 32 200 40 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 source 11.943 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to source register is 11.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X10_Y13_N7 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N7; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.935 ns) 7.648 ns clock_6:inst\|clk1hz 3 REG LC_X8_Y13_N6 19 " "Info: 3: + IC(4.000 ns) + CELL(0.935 ns) = 7.648 ns; Loc. = LC_X8_Y13_N6; Fanout = 19; REG Node = 'clock_6:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.935 ns" { clock_6:inst|clk1khz clock_6:inst|clk1hz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 11.943 ns clock_6:inst\|sec\[3\] 4 REG LC_X32_Y16_N2 13 " "Info: 4: + IC(3.584 ns) + CELL(0.711 ns) = 11.943 ns; Loc. = LC_X32_Y16_N2; Fanout = 13; REG Node = 'clock_6:inst\|sec\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { clock_6:inst|clk1hz clock_6:inst|sec[3] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.61 % ) " "Info: Total cell delay = 2.581 ns ( 21.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.362 ns ( 78.39 % ) " "Info: Total interconnect delay = 9.362 ns ( 78.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.943 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|sec[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.943 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1h