clock_6.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 register clock_6:inst\|cnt\[0\] register clock_6:inst\|\\process3:count\[5\] 42.611 ns " "Info: Slack time is 42.611 ns for clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" between source register \"clock_6:inst\|cnt\[0\]\" and destination register \"clock_6:inst\|\\process3:count\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.34 MHz 7.389 ns " "Info: Fmax is 135.34 MHz (period= 7.389 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "49.750 ns + Largest register register " "Info: + Largest register to register requirement is 49.750 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "50.000 ns + " "Info: + Setup relationship between source and destination is 50.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 47.946 ns " "Info: + Latch edge is 47.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.011 ns + Largest " "Info: + Largest clock skew is 0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 destination 7.400 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to destination register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X10_Y13_N7 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N7; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 7.400 ns clock_6:inst\|\\process3:count\[5\] 3 REG LC_X29_Y16_N4 4 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 7.400 ns; Loc. = LC_X29_Y16_N4; Fanout = 4; REG Node = 'clock_6:inst\|\\process3:count\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.687 ns" { clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.24 % ) " "Info: Total cell delay = 1.646 ns ( 22.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.754 ns ( 77.76 % ) " "Info: Total interconnect delay = 5.754 ns ( 77.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.976ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 source 7.389 ns - Longest register " "Info: - Longest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to source register is 7.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X10_Y13_N7 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X10_Y13_N7; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.965 ns) + CELL(0.711 ns) 7.389 ns clock_6:inst\|cnt\[0\] 3 REG LC_X1_Y12_N9 23 " "Info: 3: + IC(3.965 ns) + CELL(0.711 ns) = 7.389 ns; Loc. = LC_X1_Y12_N9; Fanout = 23; REG Node = 'clock_6:inst\|cnt\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.676 ns" { clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 22.28 % ) " "Info: Total cell delay = 1.646 ns ( 22.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.743 ns ( 77.72 % ) " "Info: Total interconnect delay = 5.743 ns ( 77.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.965ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.976ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.965ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.976ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.965ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.139 ns - Longest register register " "Info: - Longest register to register delay is 7.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_6:inst\|cnt\[0\] 1 REG LC_X1_Y12_N9 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y12_N9; Fanout = 23; REG Node = 'clock_6:inst\|cnt\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|cnt[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 194 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.066 ns) + CELL(0.423 ns) 4.489 ns clock_6:inst\|Add2~122 2 COMB LC_X29_Y17_N1 2 " "Info: 2: + IC(4.066 ns) + CELL(0.423 ns) = 4.489 ns; Loc. = LC_X29_Y17_N1; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~122'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.489 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.567 ns clock_6:inst\|Add2~124 3 COMB LC_X29_Y17_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 4.567 ns; Loc. = LC_X29_Y17_N2; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~124'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { clock_6:inst|Add2~122 clock_6:inst|Add2~124 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.645 ns clock_6:inst\|Add2~120 4 COMB LC_X29_Y17_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 4.645 ns; Loc. = LC_X29_Y17_N3; Fanout = 2; COMB Node = 'clock_6:inst\|Add2~120'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { clock_6:inst|Add2~124 clock_6:inst|Add2~120 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 4.823 ns clock_6:inst\|Add2~126 5 COMB LC_X29_Y17_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 4.823 ns; Loc. = LC_X29_Y17_N4; Fanout = 3; COMB Node = 'clock_6:inst\|Add2~126'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { clock_6:inst|Add2~120 clock_6:inst|Add2~126 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 5.444 ns clock_6:inst\|Add2~127 6 COMB LC_X29_Y17_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 5.444 ns; Loc. = LC_X29_Y17_N5; Fanout = 1; COMB Node = 'clock_6:inst\|Add2~127'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { clock_6:inst|Add2~126 clock_6:inst|Add2~127 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.217 ns) + CELL(0.478 ns) 7.139 ns clock_6:inst\|\\process3:count\[5\] 7 REG LC_X29_Y16_N4 4 " "Info: 7: + IC(1.217 ns) + CELL(0.478 ns) = 7.139 ns; Loc. = LC_X29_Y16_N4; Fanout = 4; REG Node = 'clock_6:inst\|\\process3:count\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.856 ns ( 26.00 % ) " "Info: Total cell delay = 1.856 ns ( 26.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.283 ns ( 74.00 % ) " "Info: Total interconnect delay = 5.283 ns ( 74.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.139 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 clock_6:inst|Add2~124 clock_6:inst|Add2~120 clock_6:inst|Add2~126 clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.139 ns" { clock_6:inst|cnt[0] {} clock_6:inst|Add2~122 {} clock_6:inst|Add2~124 {} clock_6:inst|Add2~120 {} clock_6:inst|Add2~126 {} clock_6:inst|Add2~127 {} clock_6:inst|\process3:count[5] {} } { 0.000ns 4.066ns 0.000ns 0.000ns 0.000ns 0.000ns 1.217ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|\process3:count[5] {} } { 0.000ns 1.778ns 3.976ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|cnt[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.389 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|cnt[0] {} } { 0.000ns 1.778ns 3.965ns } { 0.000ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.139 ns" { clock_6:inst|cnt[0] clock_6:inst|Add2~122 clock_6:inst|Add2~124 clock_6:inst|Add2~120 clock_6:inst|Add2~126 clock_6:inst|Add2~127 clock_6:inst|\process3:count[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.139 ns" { clock_6:inst|cnt[0] {} clock_6:inst|Add2~122 {} clock_6:inst|Add2~124 {} clock_6:inst|Add2~120 {} clock_6:inst|Add2~126 {} clock_6:inst|Add2~127 {} clock_6:inst|\process3:count[5] {} } { 0.000ns 4.066ns 0.000ns 0.000ns 0.000ns 0.000ns 1.217ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}