prev_cmp_clock_6.tan.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register clock_6:inst\|state\[0\] clock_6:inst\|state\[1\] 275.03 MHz Internal " "Info: Clock \"mode\" Internal fmax is restricted to 275.03 MHz between source register \"clock_6:inst\|state\[0\]\" and destination register \"clock_6:inst\|state\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.437 ns + Longest register register " "Info: + Longest register to register delay is 1.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_6:inst\|state\[0\] 1 REG LC_X30_Y18_N9 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y18_N9; Fanout = 14; REG Node = 'clock_6:inst\|state\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|state[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.738 ns) 1.437 ns clock_6:inst\|state\[1\] 2 REG LC_X30_Y18_N2 13 " "Info: 2: + IC(0.699 ns) + CELL(0.738 ns) = 1.437 ns; Loc. = LC_X30_Y18_N2; Fanout = 13; REG Node = 'clock_6:inst\|state\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clock_6:inst|state[0] clock_6:inst|state[1] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 51.36 % ) " "Info: Total cell delay = 0.738 ns ( 51.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.699 ns ( 48.64 % ) " "Info: Total interconnect delay = 0.699 ns ( 48.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clock_6:inst|state[0] clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.437 ns" { clock_6:inst|state[0] {} clock_6:inst|state[1] {} } { 0.000ns 0.699ns } { 0.000ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 8.141 ns + Shortest register " "Info: + Shortest clock path from clock \"mode\" to destination register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mode 1 CLK PIN_121 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 2; CLK Node = 'mode'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.961 ns) + CELL(0.711 ns) 8.141 ns clock_6:inst\|state\[1\] 2 REG LC_X30_Y18_N2 13 " "Info: 2: + IC(5.961 ns) + CELL(0.711 ns) = 8.141 ns; Loc. = LC_X30_Y18_N2; Fanout = 13; REG Node = 'clock_6:inst\|state\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.78 % ) " "Info: Total cell delay = 2.180 ns ( 26.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.961 ns ( 73.22 % ) " "Info: Total interconnect delay = 5.961 ns ( 73.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[1] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 8.141 ns - Longest register " "Info: - Longest clock path from clock \"mode\" to source register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mode 1 CLK PIN_121 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 2; CLK Node = 'mode'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 232 88 256 248 "mode" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.961 ns) + CELL(0.711 ns) 8.141 ns clock_6:inst\|state\[0\] 2 REG LC_X30_Y18_N9 14 " "Info: 2: + IC(5.961 ns) + CELL(0.711 ns) = 8.141 ns; Loc. = LC_X30_Y18_N9; Fanout = 14; REG Node = 'clock_6:inst\|state\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.78 % ) " "Info: Total cell delay = 2.180 ns ( 26.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.961 ns ( 73.22 % ) " "Info: Total interconnect delay = 5.961 ns ( 73.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[0] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[1] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[0] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { clock_6:inst|state[0] clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.437 ns" { clock_6:inst|state[0] {} clock_6:inst|state[1] {} } { 0.000ns 0.699ns } { 0.000ns 0.738ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[1] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { mode clock_6:inst|state[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { mode {} mode~out0 {} clock_6:inst|state[0] {} } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|state[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { clock_6:inst|state[1] {} } {  } {  } "" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 57 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 register clock_6:inst\|min\[4\] register clock_6:inst\|min\[4\] 1.154 ns " "Info: Minimum slack time is 1.154 ns for clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" between source register \"clock_6:inst\|min\[4\]\" and destination register \"clock_6:inst\|min\[4\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.945 ns + Shortest register register " "Info: + Shortest register to register delay is 0.945 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_6:inst\|min\[4\] 1 REG LC_X30_Y19_N6 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y19_N6; Fanout = 15; REG Node = 'clock_6:inst\|min\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_6:inst|min[4] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.309 ns) 0.945 ns clock_6:inst\|min\[4\] 2 REG LC_X30_Y19_N6 15 " "Info: 2: + IC(0.636 ns) + CELL(0.309 ns) = 0.945 ns; Loc. = LC_X30_Y19_N6; Fanout = 15; REG Node = 'clock_6:inst\|min\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { clock_6:inst|min[4] clock_6:inst|min[4] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 32.70 % ) " "Info: Total cell delay = 0.309 ns ( 32.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.636 ns ( 67.30 % ) " "Info: Total interconnect delay = 0.636 ns ( 67.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { clock_6:inst|min[4] clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.945 ns" { clock_6:inst|min[4] {} clock_6:inst|min[4] {} } { 0.000ns 0.636ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst2\|altpll:altpll_component\|_clk0 50.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is 50.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 destination 11.920 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to destination register is 11.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X8_Y13_N6 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.614 ns) + CELL(0.935 ns) 7.262 ns clock_6:inst\|clk1hz 3 REG LC_X9_Y13_N2 19 " "Info: 3: + IC(3.614 ns) + CELL(0.935 ns) = 7.262 ns; Loc. = LC_X9_Y13_N2; Fanout = 19; REG Node = 'clock_6:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.549 ns" { clock_6:inst|clk1khz clock_6:inst|clk1hz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.947 ns) + CELL(0.711 ns) 11.920 ns clock_6:inst\|min\[4\] 4 REG LC_X30_Y19_N6 15 " "Info: 4: + IC(3.947 ns) + CELL(0.711 ns) = 11.920 ns; Loc. = LC_X30_Y19_N6; Fanout = 15; REG Node = 'clock_6:inst\|min\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.658 ns" { clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.65 % ) " "Info: Total cell delay = 2.581 ns ( 21.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.339 ns ( 78.35 % ) " "Info: Total interconnect delay = 9.339 ns ( 78.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 source 11.920 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to source register is 11.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X8_Y13_N6 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.614 ns) + CELL(0.935 ns) 7.262 ns clock_6:inst\|clk1hz 3 REG LC_X9_Y13_N2 19 " "Info: 3: + IC(3.614 ns) + CELL(0.935 ns) = 7.262 ns; Loc. = LC_X9_Y13_N2; Fanout = 19; REG Node = 'clock_6:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.549 ns" { clock_6:inst|clk1khz clock_6:inst|clk1hz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.947 ns) + CELL(0.711 ns) 11.920 ns clock_6:inst\|min\[4\] 4 REG LC_X30_Y19_N6 15 " "Info: 4: + IC(3.947 ns) + CELL(0.711 ns) = 11.920 ns; Loc. = LC_X30_Y19_N6; Fanout = 15; REG Node = 'clock_6:inst\|min\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.658 ns" { clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.65 % ) " "Info: Total cell delay = 2.581 ns ( 21.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.339 ns ( 78.35 % ) " "Info: Total interconnect delay = 9.339 ns ( 78.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { clock_6:inst|min[4] clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.945 ns" { clock_6:inst|min[4] {} clock_6:inst|min[4] {} } { 0.000ns 0.636ns } { 0.000ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[4] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clock_6:inst\|min\[0\] inc clk 4.890 ns register " "Info: tsu for register \"clock_6:inst\|min\[0\]\" (data pin = \"inc\", clock pin = \"clk\") is 4.890 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.719 ns + Longest pin register " "Info: + Longest pin to register delay is 14.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inc 1 PIN PIN_123 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 2; PIN Node = 'inc'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inc } "NODE_NAME" } } { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 248 88 256 264 "inc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.846 ns) + CELL(0.590 ns) 10.905 ns clock_6:inst\|hour\[4\]~189 2 COMB LC_X31_Y17_N8 3 " "Info: 2: + IC(8.846 ns) + CELL(0.590 ns) = 10.905 ns; Loc. = LC_X31_Y17_N8; Fanout = 3; COMB Node = 'clock_6:inst\|hour\[4\]~189'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.436 ns" { inc clock_6:inst|hour[4]~189 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.227 ns) + CELL(0.442 ns) 12.574 ns clock_6:inst\|min\[5\]~193 3 COMB LC_X31_Y18_N0 6 " "Info: 3: + IC(1.227 ns) + CELL(0.442 ns) = 12.574 ns; Loc. = LC_X31_Y18_N0; Fanout = 6; COMB Node = 'clock_6:inst\|min\[5\]~193'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { clock_6:inst|hour[4]~189 clock_6:inst|min[5]~193 } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(0.867 ns) 14.719 ns clock_6:inst\|min\[0\] 4 REG LC_X31_Y19_N8 5 " "Info: 4: + IC(1.278 ns) + CELL(0.867 ns) = 14.719 ns; Loc. = LC_X31_Y19_N8; Fanout = 5; REG Node = 'clock_6:inst\|min\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.145 ns" { clock_6:inst|min[5]~193 clock_6:inst|min[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.368 ns ( 22.88 % ) " "Info: Total cell delay = 3.368 ns ( 22.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.351 ns ( 77.12 % ) " "Info: Total interconnect delay = 11.351 ns ( 77.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.719 ns" { inc clock_6:inst|hour[4]~189 clock_6:inst|min[5]~193 clock_6:inst|min[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.719 ns" { inc {} inc~out0 {} clock_6:inst|hour[4]~189 {} clock_6:inst|min[5]~193 {} clock_6:inst|min[0] {} } { 0.000ns 0.000ns 8.846ns 1.227ns 1.278ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk altpll0:inst2\|altpll:altpll_component\|_clk0 -2.054 ns - " "Info: - Offset between input clock \"clk\" and output clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 24 32 200 40 "clk" "" } } } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst2\|altpll:altpll_component\|_clk0 destination 11.920 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst2\|altpll:altpll_component\|_clk0\" to destination register is 11.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 15; CLK Node = 'altpll0:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(0.935 ns) 2.713 ns clock_6:inst\|clk1khz 2 REG LC_X8_Y13_N6 21 " "Info: 2: + IC(1.778 ns) + CELL(0.935 ns) = 2.713 ns; Loc. = LC_X8_Y13_N6; Fanout = 21; REG Node = 'clock_6:inst\|clk1khz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.614 ns) + CELL(0.935 ns) 7.262 ns clock_6:inst\|clk1hz 3 REG LC_X9_Y13_N2 19 " "Info: 3: + IC(3.614 ns) + CELL(0.935 ns) = 7.262 ns; Loc. = LC_X9_Y13_N2; Fanout = 19; REG Node = 'clock_6:inst\|clk1hz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.549 ns" { clock_6:inst|clk1khz clock_6:inst|clk1hz } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.947 ns) + CELL(0.711 ns) 11.920 ns clock_6:inst\|min\[0\] 4 REG LC_X31_Y19_N8 5 " "Info: 4: + IC(3.947 ns) + CELL(0.711 ns) = 11.920 ns; Loc. = LC_X31_Y19_N8; Fanout = 5; REG Node = 'clock_6:inst\|min\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.658 ns" { clock_6:inst|clk1hz clock_6:inst|min[0] } "NODE_NAME" } } { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 21.65 % ) " "Info: Total cell delay = 2.581 ns ( 21.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.339 ns ( 78.35 % ) " "Info: Total interconnect delay = 9.339 ns ( 78.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[0] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.719 ns" { inc clock_6:inst|hour[4]~189 clock_6:inst|min[5]~193 clock_6:inst|min[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.719 ns" { inc {} inc~out0 {} clock_6:inst|hour[4]~189 {} clock_6:inst|min[5]~193 {} clock_6:inst|min[0] {} } { 0.000ns 0.000ns 8.846ns 1.227ns 1.278ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 clock_6:inst|clk1khz clock_6:inst|clk1hz clock_6:inst|min[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.920 ns" { altpll0:inst2|altpll:altpll_component|_clk0 {} clock_6:inst|clk1khz {} clock_6:inst|clk1hz {} clock_6:inst|min[0] {} } { 0.000ns 1.778ns 3.614ns 3.947ns } { 0.000ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}