clock_6.map.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 10:02:29 2008 " "Info: Processing started: Sun May 18 10:02:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock_6 -c clock_6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock_6 -c clock_6" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altpll0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file altpll0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altpll0-SYN " "Info: Found design unit 1: altpll0-SYN" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/altpll0.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/altpll0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock_6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_6-one " "Info: Found design unit 1: clock_6-one" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clock_6 " "Info: Found entity 1: clock_6" {  } { { "clock_6.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_6_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_6_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock_6_test " "Info: Found entity 1: clock_6_test" {  } { { "clock_6_test.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock_6_test " "Info: Elaborating entity \"clock_6_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_6 clock_6:inst " "Info: Elaborating entity \"clock_6\" for hierarchy \"clock_6:inst\"" {  } { { "clock_6_test.bdf" "inst" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { 160 272 400 288 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst2 " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst2\"" {  } { { "clock_6_test.bdf" "inst2" { Schematic "D:/lecture/embed/FPGA/FPGAExample/clock_6/clock_6_test.bdf" { { -32 216 456 128 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0:inst2\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0:inst2\|altpll:altpll_component\"" {  } { { "altpll0.vhd" "altpll_component" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/altpll0.vhd" 128 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll0:inst2\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll0:inst2\|altpll:altpll_component\"" {  } { { "altpll0.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/clock_6/altpll0.vhd" 128 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clock_6:inst\|\\process3:count\[0\] clock_6:inst\|cnt\[0\] " "Info: Duplicate register \"clock_6:inst\|\\process3:count\[0\]\" merged to single register \"clock_6:inst\|cnt\[0\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "clock_6:inst\|\\process2:count\[0\] clock_6:inst\|cnt\[0\] " "Info: Duplicate register \"clock_6:inst\|\\process2:count\[0\]\" merged to single register \"clock_6:inst\|cnt\[0\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "213 " "Info: Implemented 213 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "194 " "Info: Implemented 194 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 10:02:38 2008 " "Info: Processing ended: Sun May 18 10:02:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}