clock_6.tan.rpt

来自「FPGA和VHDL的全过程和源码」· RPT 代码 · 共 256 行 · 第 1/5 页

; Total number of failed paths                               ;           ;                                  ;                                                ;                       ;                                 ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-----------------------+---------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; altpll0:inst2|altpll:altpll_component|_clk0 ;                    ; PLL output ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 2                     ; 5                   ; -2.054 ns ;              ;
; clk                                         ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; mode                                        ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altpll0:inst2|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+---------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                            ; To                              ; From Clock                                  ; To Clock                                    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------+---------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 42.611 ns                               ; 135.34 MHz ( period = 7.389 ns )                    ; clock_6:inst|cnt[0]             ; clock_6:inst|\process3:count[5] ; altpll0:inst2|altpll:altpll_component|_clk0 ; altpll0:inst2|altpll:altpll_component|_clk0 ; 50.000 ns                   ; 49.750 ns                 ; 7.139 ns                ;
; 42.738 ns                               ; 137.70 MHz ( period = 7.262 ns )                    ; clock_6:inst|cnt[0]             ; clock_6:inst|\process3:count[6] ; altpll0:inst2|altpll:altpll_component|_clk0 ; altpll0:inst2|altpll:altpll_component|_clk0 ; 50.000 ns                   ; 49.750 ns                 ; 7.012 ns                ;
; 42.976 ns                               ; 142.37 MHz ( period = 7.024 ns )                    ; clock_6:inst|cnt[0]             ; clock_6:inst|\process3:count[4] ; altpll0:inst2|altpll:altpll_component|_clk0 ; altpll0:inst2|altpll:altpll_component|_clk0 ; 50.000 ns                   ; 49.750 ns                 ; 6.774 ns                ;
; 43.047 ns                               ; 143.82 MHz ( period = 6.953 ns )                    ; clock_6:inst|cnt[0]             ; clock_6:inst|\process3:count[3] ; altpll0:inst2|altpll:altpll_component|_clk0 ; altpll0:inst2|altpll:altpll_component|_clk0 ; 50.000 ns                   ; 49.750 ns                 ; 6.703 ns                ;