clock_6.map.summary

FPGA和VHDL的全过程和源码

Analysis & Synthesis Status : Successful - Sun May 18 10:02:38 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : clock_6
Top-level Entity Name : clock_6_test
Family : Cyclone
Total logic elements : 194
Total pins : 18
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 1
Total DLLs : N/A until Partition Merge