📄 x_detect.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--p.s8 is p.s8
p.s8 = DFFEAS(A1L10, clk, , , , , , , );
--p.s7 is p.s7
p.s7 = DFFEAS(A1L9, clk, , , , , , , );
--A1L10 is n.s8~1
A1L10 = !data & p.s7;
--p.s6 is p.s6
p.s6 = DFFEAS(A1L8, clk, , , , , , , );
--A1L9 is n.s7~8
A1L9 = data & p.s6;
--p.s5 is p.s5
p.s5 = DFFEAS(A1L7, clk, , , , , , , );
--A1L8 is n.s6~1
A1L8 = !data & p.s5;
--p.s4 is p.s4
p.s4 = DFFEAS(A1L6, clk, , , , , , , );
--A1L7 is n.s5~1
A1L7 = !data & p.s4;
--p.s3 is p.s3
p.s3 = DFFEAS(A1L5, clk, , , , , , , );
--A1L6 is n.s4~17
A1L6 = data & (p.s4 # p.s3);
--p.s2 is p.s2
p.s2 = DFFEAS(A1L4, clk, , , , , , , );
--A1L5 is n.s3~17
A1L5 = data & (p.s7 # p.s2);
--p.s1 is p.s1
p.s1 = DFFEAS(A1L3, clk, , , , , , , );
--A1L4 is n.s2~32
A1L4 = data & (p.s8 # p.s5 # !p.s1);
--A1L3 is n.s1~20
A1L3 = p.s7 # data # p.s5 # p.s4;
--data is data
--operation mode is input
data = INPUT();
--clk is clk
--operation mode is input
clk = INPUT();
--y is y
--operation mode is output
y = OUTPUT(p.s8);
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