x_detect.tan.rpt

statemachine it can detecate statemachine

; N/A   ; None         ; -0.710 ns  ; data ; p.s7 ; clk      ;
; N/A   ; None         ; -0.715 ns  ; data ; p.s2 ; clk      ;
; N/A   ; None         ; -0.716 ns  ; data ; p.s8 ; clk      ;
; N/A   ; None         ; -0.717 ns  ; data ; p.s5 ; clk      ;
; N/A   ; None         ; -0.718 ns  ; data ; p.s4 ; clk      ;
; N/A   ; None         ; -0.724 ns  ; data ; p.s6 ; clk      ;
+-------+--------------+------------+------+------+----------+


+------------------------------------------------------------+
; tco                                                        ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A   ; None         ; 7.570 ns   ; p.s8 ; y  ; clk        ;
+-------+--------------+------------+------+----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; 0.990 ns  ; data ; p.s6 ; clk      ;
; N/A           ; None        ; 0.984 ns  ; data ; p.s4 ; clk      ;
; N/A           ; None        ; 0.983 ns  ; data ; p.s5 ; clk      ;
; N/A           ; None        ; 0.982 ns  ; data ; p.s8 ; clk      ;
; N/A           ; None        ; 0.981 ns  ; data ; p.s2 ; clk      ;
; N/A           ; None        ; 0.976 ns  ; data ; p.s7 ; clk      ;
; N/A           ; None        ; 0.975 ns  ; data ; p.s3 ; clk      ;
; N/A           ; None        ; 0.975 ns  ; data ; p.s1 ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri May 09 19:45:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off x_detect -c x_detect --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "p.s7" and destination register "p.s8"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.236 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N7; Fanout = 3; REG Node = 'p.s7'
            Info: 2: + IC(0.477 ns) + CELL(0.651 ns) = 1.128 ns; Loc. = LCCOMB_X30_Y35_N12; Fanout = 1; COMB Node = 'n.s8~1'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.236 ns; Loc. = LCFF_X30_Y35_N13; Fanout = 2; REG Node = 'p.s8'
            Info: Total cell delay = 0.759 ns ( 61.41 % )
            Info: Total interconnect delay = 0.477 ns ( 38.59 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.120 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.215 ns) + CELL(0.666 ns) = 3.120 ns; Loc. = LCFF_X30_Y35_N13; Fanout = 2; REG Node = 'p.s8'
                Info: Total cell delay = 1.766 ns ( 56.60 % )
                Info: Total interconnect delay = 1.354 ns ( 43.40 % )
            Info: - Longest clock path from clock "clk" to source register is 3.120 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.215 ns) + CELL(0.666 ns) = 3.120 ns; Loc. = LCFF_X30_Y35_N7; Fanout = 3; REG Node = 'p.s7'
                Info: Total cell delay = 1.766 ns ( 56.60 % )
                Info: Total interconnect delay = 1.354 ns ( 43.40 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "p.s3" (data pin = "data", clock pin = "clk") is -0.709 ns
    Info: + Longest pin to register delay is 2.451 ns
        Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_C13; Fanout = 8; PIN Node = 'data'
        Info: 2: + IC(1.057 ns) + CELL(0.206 ns) = 2.343 ns; Loc. = LCCOMB_X30_Y35_N0; Fanout = 1; COMB Node = 'n.s3~17'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.451 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'p.s3'
        Info: Total cell delay = 1.394 ns ( 56.87 % )
        Info: Total interconnect delay = 1.057 ns ( 43.13 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.120 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.215 ns) + CELL(0.666 ns) = 3.120 ns; Loc. = LCFF_X30_Y35_N1; Fanout = 1; REG Node = 'p.s3'
        Info: Total cell delay = 1.766 ns ( 56.60 % )
        Info: Total interconnect delay = 1.354 ns ( 43.40 % )
Info: tco from clock "clk" to destination pin "y" through register "p.s8" is 7.570 ns
    Info: + Longest clock path from clock "clk" to source register is 3.120 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.215 ns) + CELL(0.666 ns) = 3.120 ns; Loc. = LCFF_X30_Y35_N13; Fanout = 2; REG Node = 'p.s8'
        Info: Total cell delay = 1.766 ns ( 56.60 % )
        Info: Total interconnect delay = 1.354 ns ( 43.40 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.146 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y35_N13; Fanout = 2; REG Node = 'p.s8'
        Info: 2: + IC(0.920 ns) + CELL(3.226 ns) = 4.146 ns; Loc. = PIN_B12; Fanout = 0; PIN Node = 'y'
        Info: Total cell delay = 3.226 ns ( 77.81 % )
        Info: Total interconnect delay = 0.920 ns ( 22.19 % )
Info: th for register "p.s6" (data pin = "data", clock pin = "clk") is 0.990 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.120 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.215 ns) + CELL(0.666 ns) = 3.120 ns; Loc. = LCFF_X30_Y35_N19; Fanout = 1; REG Node = 'p.s6'
        Info: Total cell delay = 1.766 ns ( 56.60 % )
        Info: Total interconnect delay = 1.354 ns ( 43.40 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.436 ns
        Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_C13; Fanout = 8; PIN Node = 'data'
        Info: 2: + IC(1.046 ns) + CELL(0.202 ns) = 2.328 ns; Loc. = LCCOMB_X30_Y35_N18; Fanout = 1; COMB Node = 'n.s6~1'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.436 ns; Loc. = LCFF_X30_Y35_N19; Fanout = 1; REG Node = 'p.s6'
        Info: Total cell delay = 1.390 ns ( 57.06 % )
        Info: Total interconnect delay = 1.046 ns ( 42.94 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri May 09 19:45:27 2008
    Info: Elapsed time: 00:00:02