sram_2.map.rpt
来自「8x8DCT verilog code 一次輸入8個點」· RPT 代码 · 共 309 行 · 第 1/5 页
RPT
309 行
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ; work ;
; |sld_jtag_state_machine:jtag_state_machine| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ; work ;
; |sld_rom_sr:HUB_INFO_REG| ; 17 (17) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ; work ;
; |sld_signaltap:auto_signaltap_0| ; 422 (0) ; 808 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0 ; work ;
; |sld_signaltap_impl:sld_signaltap_body| ; 422 (6) ; 808 (172) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; work ;
; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ;
; |altsyncram_eui2:auto_generated| ; 0 (0) ; 0 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_eui2:auto_generated ; work ;
; |altsyncram_p4l1:altsyncram1| ; 0 (0) ; 0 (0) ; 344064 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_eui2:auto_generated|altsyncram_p4l1:altsyncram1 ; work ;
; |sld_acquisition_buffer:sld_acquisition_buffer_inst| ; 16 (3) ; 25 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst ; work ;
; |lpm_counter:\write_address_non_zero_gen:write_pointer_counter| ; 13 (0) ; 12 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter ; work ;
; |cntr_hmk:auto_generated| ; 13 (13) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_hmk:auto_generated ; work ;
; |lpm_ff:\gen_non_zero_sample_depth:trigger_address_register| ; 0 (0) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register ; work ;
; |sld_ela_control:ela_control| ; 246 (5) ; 475 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 168 (0) ; 420 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 252 (252) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 168 (0) ; 168 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |SRAM_2|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_m⌨️ 快捷键说明
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