b4dm.v

来自「8x8DCT verilog code 一次輸入8個點」· Verilog 代码 · 共 23 行

module B4DM(A, B, S);
	
	parameter n = 8;
	
	input [n+1:0]A;
	input [3:0]B;
	
	output [n+1:0]S;
	
	// --------------- * 
	
	wire [n+1:0]Ax1,Ax2,Ax3,Ax4;
	
	assign Ax1 = (B[3] == 1'b1)? {{1{A[n+1]}},A[n+1:1]} : 10'b0;
	assign Ax2 = (B[2] == 1'b1)? {{2{A[n+1]}},A[n+1:2]} : 10'b0;
	assign Ax3 = (B[1] == 1'b1)? {{3{A[n+1]}},A[n+1:3]} : 10'b0;
	assign Ax4 = (B[0] == 1'b1)? {{4{A[n+1]}},A[n+1:4]} : 10'b0;

	assign S = Ax1 +Ax2 +Ax3 +Ax4;
	
	// --------------- * 
		
endmodule