altsyncram_nmi1.tdf

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TDF
1,876 行
字号
12345
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a49 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a50 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a51 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a52 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a53 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a54 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a55 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a56 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a57 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a58 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a59 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a60 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 3,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_LAST_ADDRESS = 7,
			PORT_A_LOGICAL_RAM_DEPTH = 8,
			PORT_A_LOGICAL_RAM_WIDTH = 96,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 3,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 60,
			PORT_B_LAST_ADDRESS = 7,
			PORT_B_LOGICAL_RAM_DEPTH = 8,
			PORT_B_LOGICAL_RAM_WIDTH = 96,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a61 : cyclon
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altsyncram_nmi1.tdf - 源码说明

本页面展示了「8x8DCT verilog code 一次輸入8個點」中的 altsyncram_nmi1.tdf 源码文件，采用 TDF 编程语言编写，共 1,876 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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