📄 pwm_gen.map.rpt
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; CBXI_PARAMETER ; add_sub_ioh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pwm_counter:inst|lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+--------------------------------------------------+
; LPM_WIDTH ; 22 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_koh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pwm_counter:inst|lpm_add_sub:add_rtl_4 ;
+------------------------+-------------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+--------------------------------------------------+
; LPM_WIDTH ; 5 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_2nh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/03-源码文件/VHDL/13-PWM信号产生/pwm_gen.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Mar 26 11:14:33 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwm_gen -c pwm_gen
Info: Found 2 design units, including 1 entities, in source file counter.vhd
Info: Found design unit 1: counter-counter_architecture
Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file pwm.vhd
Info: Found design unit 1: pwm-pwm_architecture
Info: Found entity 1: pwm
Info: Found 1 design units, including 1 entities, in source file pwm_gen.bdf
Info: Found entity 1: pwm_gen
Info: Found 2 design units, including 1 entities, in source file serialport_tx.vhd
Info: Found design unit 1: serialport_tx-serialport_tx_architecture
Info: Found entity 1: serialport_tx
Info: Found 2 design units, including 1 entities, in source file pwm_counter.vhd
Info: Found design unit 1: pwm_counter-pwm_architecture
Info: Found entity 1: pwm_counter
Info: Elaborating entity "pwm_gen" for the top level hierarchy
Warning: Port "carrier" of type counter and instance "inst3" is missing source signal
Warning: Port "counter" of type counter and instance "inst3" is missing source signal
Info: Elaborating entity "serialport_tx" for hierarchy "serialport_tx:inst5"
Info (10035): Verilog HDL or VHDL information at serialport_tx.vhd(62): object "tmp" declared but not used
Info: Elaborating entity "pwm" for hierarchy "pwm:inst4"
Info: Elaborating entity "pwm_counter" for hierarchy "pwm_counter:inst"
Info (10425): VHDL Case Statement information at pwm_counter.vhd(118): OTHERS choice is never selected
Info: Elaborating entity "counter" for hierarchy "counter:inst3"
Warning: Reduced register "serialport_tx:inst5|idata[7]" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "pwm:inst4|delay_counter[0]~64"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 55 buffer(s)
Info: Ignored 55 SOFT buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register "counter:inst3|delay_counter[0]" merged to single register "pwm_counter:inst|delay_counter[0]"
Info: Duplicate register "pwm_counter:inst|send_counter[0]" merged to single register "pwm_counter:inst|delay_counter[0]"
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
Warning: Pin "Vref" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clock_24M" to global clock signal
Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Implemented 124 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 3 output pins
Info: Implemented 116 macrocells
Info: Implemented 3 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Mon Mar 26 11:14:44 2007
Info: Elapsed time: 00:00:12
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