keyboard1.tan.qmsg

数码管显示Vhdl实现

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "delay_kbtingle:inst4\|previous_row_data\[0\]~42 " "Info: Node \"delay_kbtingle:inst4\|previous_row_data\[0\]~42\"" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "delay_kbtingle:inst4\|previous_row_data\[2\]~48 " "Info: Node \"delay_kbtingle:inst4\|previous_row_data\[2\]~48\"" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "delay_kbtingle:inst4\|previous_row_data\[1\]~45 " "Info: Node \"delay_kbtingle:inst4\|previous_row_data\[1\]~45\"" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock_1k " "Info: Assuming node \"clock_1k\" is an undefined clock" {  } { { "keyboard1.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.bdf" { { -24 200 368 -8 "clock_1k" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock_1k" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "row_data\[0\] " "Info: Assuming node \"row_data\[0\]\" is an undefined clock" {  } { { "keyboard1.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.bdf" { { 440 -96 72 456 "row_data\[3..0\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "row_data\[0\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "row_data\[1\] " "Info: Assuming node \"row_data\[1\]\" is an undefined clock" {  } { { "keyboard1.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.bdf" { { 440 -96 72 456 "row_data\[3..0\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "row_data\[1\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "row_data\[2\] " "Info: Assuming node \"row_data\[2\]\" is an undefined clock" {  } { { "keyboard1.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.bdf" { { 440 -96 72 456 "row_data\[3..0\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "row_data\[2\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "row_data\[3\] " "Info: Assuming node \"row_data\[3\]\" is an undefined clock" {  } { { "keyboard1.bdf" "" { Schematic "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/keyboard1.bdf" { { 440 -96 72 456 "row_data\[3..0\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "row_data\[3\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "36 " "Warning: Found 36 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~479 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~479\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~479" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~478 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~478\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~478" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~477 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~477\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~477" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~476 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~476\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~476" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~475 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~475\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~475" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~474 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~474\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~474" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~473 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~473\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~473" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~472 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~472\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~472" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~471 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~471\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~471" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~470 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~470\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~470" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~469 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~469\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~469" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~468 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~468\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~468" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~467 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~467\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~467" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~466 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~466\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~466" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~465 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~465\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~465" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~464 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~464\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~464" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~463 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~463\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~463" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~462 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~462\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~462" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~321 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~321\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~321" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~320 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~320\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~320" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~319 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~319\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~319" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~318 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~318\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~318" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~317 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~317\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~317" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|key_down~316 " "Info: Detected gated clock \"delay_kbtingle:inst4\|key_down~316\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 47 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|key_down~316" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst2\|carrier " "Info: Detected ripple clock \"counter:inst2\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/counter.vhd" 50 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst2\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter:inst1\|carrier " "Info: Detected ripple clock \"counter:inst1\|carrier\" as buffer" {  } { { "counter.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/counter.vhd" 50 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter:inst1\|carrier" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|previous_row_data\[3\]~51 " "Info: Detected gated clock \"delay_kbtingle:inst4\|previous_row_data\[3\]~51\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|previous_row_data\[3\]~51" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|previous_row_data\[0\]~42 " "Info: Detected gated clock \"delay_kbtingle:inst4\|previous_row_data\[0\]~42\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|previous_row_data\[0\]~42" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|previous_row_data\[2\]~48 " "Info: Detected gated clock \"delay_kbtingle:inst4\|previous_row_data\[2\]~48\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|previous_row_data\[2\]~48" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|previous_row_data\[1\]~45 " "Info: Detected gated clock \"delay_kbtingle:inst4\|previous_row_data\[1\]~45\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 71 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|previous_row_data\[1\]~45" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[1\] " "Info: Detected ripple clock \"delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[1\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 285 12 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[0\] " "Info: Detected ripple clock \"delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[0\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 285 12 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[2\] " "Info: Detected ripple clock \"delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[2\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 285 12 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[3\] " "Info: Detected ripple clock \"delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[3\]\" as buffer" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 285 12 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|lpm_counter:currentState_rtl_0\|dffs\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "delay_kbtingle:inst4\|scan_start " "Info: Detected ripple clock \"delay_kbtingle:inst4\|scan_start\" as buffer" {  } { { "delay_kbtingle.vhd" "" { Text "U:/02-开发板/CA328/03-源码文件/VHDL/05-键盘阵列-数码管显示/delay_kbtingle.vhd" 66 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|scan_start" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "delay_kbtingle:inst4\|process0~96 " "Info: Detected gated clock \"delay_kbtingle:inst4\|process0~96\" as buffer" {  } { { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "delay_kbtingle:inst4\|process0~96" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}