eight_choose.vhd

来自「8选1数据选择器」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
entity eight_choose is
port (c1,c2,c3: in std_logic;
      a,b,c,d,e,f,g,h: in std_logic;
      z: out std_logic);
end eight_choose;
architecture example2 of eight_choose is
signal s: std_logic_vector(2 downto 0);
 begin 
    s<=c1&c2&c3;
    process(c1,c2,c3,a,b,c,d,e,f,g,h)
     begin
      case s is
        when "000"=>z<=a;
        when "001"=>z<=b;
        when "010"=>z<=c;
        when "011"=>z<=d;
        when "100"=>z<=e;
        when "101"=>z<=f;
        when "110"=>z<=g;
        when "111"=>z<=h;
     end case;
   end process;
end example2;