eight_choose.tan.rpt

8选1数据选择器

Timing Analyzer report for eight_choose
Sat Apr 05 12:39:15 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 12.354 ns   ; c2   ; z  ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 12.354 ns       ; c2   ; z  ;
; N/A   ; None              ; 12.345 ns       ; b    ; z  ;
; N/A   ; None              ; 12.249 ns       ; c3   ; z  ;
; N/A   ; None              ; 12.175 ns       ; a    ; z  ;
; N/A   ; None              ; 11.972 ns       ; g    ; z  ;
; N/A   ; None              ; 11.653 ns       ; h    ; z  ;
; N/A   ; None              ; 11.499 ns       ; e    ; z  ;
; N/A   ; None              ; 11.146 ns       ; d    ; z  ;
; N/A   ; None              ; 10.854 ns       ; c    ; z  ;
; N/A   ; None              ; 10.630 ns       ; f    ; z  ;
; N/A   ; None              ; 10.512 ns       ; c1   ; z  ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 05 12:39:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off eight_choose -c eight_choose --timing_analysis_only
Info: Longest tpd from source pin "c2" to destination pin "z" is 12.354 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_13; Fanout = 3; PIN Node = 'c2'
    Info: 2: + IC(5.100 ns) + CELL(0.442 ns) = 7.011 ns; Loc. = LC_X1_Y24_N5; Fanout = 1; COMB Node = 'Mux~12'
    Info: 3: + IC(0.400 ns) + CELL(0.442 ns) = 7.853 ns; Loc. = LC_X1_Y24_N4; Fanout = 1; COMB Node = 'Mux~13'
    Info: 4: + IC(0.399 ns) + CELL(0.442 ns) = 8.694 ns; Loc. = LC_X1_Y24_N8; Fanout = 1; COMB Node = 'Mux~16'
    Info: 5: + IC(1.536 ns) + CELL(2.124 ns) = 12.354 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'z'
    Info: Total cell delay = 4.919 ns ( 39.82 % )
    Info: Total interconnect delay = 7.435 ns ( 60.18 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Apr 05 12:39:15 2008
    Info: Elapsed time: 00:00:03