dds.map.qmsg

基于DDS的数字移相正弦信号发生器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 19 16:27:11 2008 " "Info: Processing started: Thu Jun 19 16:27:11 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SUM99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SUM99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SUM99-ART " "Info: Found design unit 1: SUM99-ART" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SUM99 " "Info: Found entity 1: SUM99" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS-ART " "Info: Found design unit 1: DDS-ART" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG1-ART " "Info: Found design unit 1: REG1-ART" {  } { { "REG1.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG1.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 REG1 " "Info: Found entity 1: REG1" {  } { { "REG1.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG1.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG2-ART " "Info: Found design unit 1: REG2-ART" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 REG2 " "Info: Found entity 1: REG2" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ROM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ROM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-ART " "Info: Found design unit 1: ROM-ART" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/ROM.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Info: Found entity 1: ROM" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/ROM.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUM99 SUM99:U0 " "Info: Elaborating entity \"SUM99\" for hierarchy \"SUM99:U0\"" {  } { { "DDS.vhd" "U0" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 39 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP SUM99.vhd(26) " "Warning: VHDL Process Statement warning at SUM99.vhd(26): signal \"TEMP\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 26 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG1 REG1:U1 " "Info: Elaborating entity \"REG1\" for hierarchy \"REG1:U1\"" {  } { { "DDS.vhd" "U1" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 40 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:U2 " "Info: Elaborating entity \"ROM\" for hierarchy \"ROM:U2\"" {  } { { "DDS.vhd" "U2" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 41 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG2 REG2:U3 " "Info: Elaborating entity \"REG2\" for hierarchy \"REG2:U3\"" {  } { { "DDS.vhd" "U3" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 42 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ROM:U2\|OUTP\[7\] ROM:U2\|OUTP\[6\] " "Info: Duplicate register \"ROM:U2\|OUTP\[7\]\" merged to single register \"ROM:U2\|OUTP\[6\]\"" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/ROM.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ROM:U2\|OUTP\[8\] ROM:U2\|OUTP\[6\] " "Info: Duplicate register \"ROM:U2\|OUTP\[8\]\" merged to single register \"ROM:U2\|OUTP\[6\]\"" {  } { { "ROM.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/ROM.vhd" 9 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG2:U3\|Q\[7\] REG2:U3\|Q\[6\] " "Info: Duplicate register \"REG2:U3\|Q\[7\]\" merged to single register \"REG2:U3\|Q\[6\]\"" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "REG2:U3\|Q\[8\] REG2:U3\|Q\[6\] " "Info: Duplicate register \"REG2:U3\|Q\[8\]\" merged to single register \"REG2:U3\|Q\[6\]\"" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "95 " "Info: Implemented 95 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "73 " "Info: Implemented 73 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 19 16:27:16 2008 " "Info: Processing ended: Thu Jun 19 16:27:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}