dds.tan.qmsg

基于DDS的数字移相正弦信号发生器设计

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[0\] REG2:U3\|Q\[0\] 14.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[0\]\" through register \"REG2:U3\|Q\[0\]\" is 14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_182 36 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns REG2:U3\|Q\[0\] 2 REG LC7_J29 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_J29; Fanout = 1; REG Node = 'REG2:U3\|Q\[0\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.400 ns" { CLK REG2:U3|Q[0] } "NODE_NAME" } "" } } { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.900 ns" { CLK REG2:U3|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out REG2:U3|Q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register pin " "Info: + Longest register to pin delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG2:U3\|Q\[0\] 1 REG LC7_J29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_J29; Fanout = 1; REG Node = 'REG2:U3\|Q\[0\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "" { REG2:U3|Q[0] } "NODE_NAME" } "" } } { "REG2.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/REG2.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(8.600 ns) 11.800 ns Q\[0\] 2 PIN PIN_19 0 " "Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'Q\[0\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "11.800 ns" { REG2:U3|Q[0] Q[0] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 72.88 % " "Info: Total cell delay = 8.600 ns ( 72.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 27.12 % " "Info: Total interconnect delay = 3.200 ns ( 27.12 % )" {  } {  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "11.800 ns" { REG2:U3|Q[0] Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.800 ns" { REG2:U3|Q[0] Q[0] } { 0.000ns 3.200ns } { 0.000ns 8.600ns } } }  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.900 ns" { CLK REG2:U3|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out REG2:U3|Q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "11.800 ns" { REG2:U3|Q[0] Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.800 ns" { REG2:U3|Q[0] Q[0] } { 0.000ns 3.200ns } { 0.000ns 8.600ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "SUM99:U0\|TEMP\[4\] K\[4\] CLK -5.600 ns register " "Info: th for register \"SUM99:U0\|TEMP\[4\]\" (data pin = \"K\[4\]\", clock pin = \"CLK\") is -5.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_182 36 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns SUM99:U0\|TEMP\[4\] 2 REG LC1_J20 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J20; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[4\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.400 ns" { CLK SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.900 ns" { CLK SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.400 ns) 3.400 ns K\[4\] 1 PIN PIN_115 2 " "Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_115; Fanout = 2; PIN Node = 'K\[4\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "" { K[4] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/DDS.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 7.200 ns SUM99:U0\|lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\] 2 COMB LC8_J20 1 " "Info: 2: + IC(1.800 ns) + CELL(2.000 ns) = 7.200 ns; Loc. = LC8_J20; Fanout = 1; COMB Node = 'SUM99:U0\|lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "3.800 ns" { K[4] SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 8.400 ns SUM99:U0\|TEMP\[4\] 3 REG LC1_J20 3 " "Info: 3: + IC(0.200 ns) + CELL(1.000 ns) = 8.400 ns; Loc. = LC1_J20; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[4\]'" {  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.200 ns" { SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "SUM99.vhd" "" { Text "C:/Documents and Settings/gdufs/桌面/DDS做/SUM99.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns 76.19 % " "Info: Total cell delay = 6.400 ns ( 76.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 23.81 % " "Info: Total interconnect delay = 2.000 ns ( 23.81 % )" {  } {  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "8.400 ns" { K[4] SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { K[4] K[4]~out SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.800ns 0.200ns } { 0.000ns 3.400ns 2.000ns 1.000ns } } }  } 0}  } { { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "1.900 ns" { CLK SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/gdufs/桌面/DDS做/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/gdufs/桌面/DDS做/" "" "8.400 ns" { K[4] SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] SUM99:U0|TEMP[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.400 ns" { K[4] K[4]~out SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.800ns 0.200ns } { 0.000ns 3.400ns 2.000ns 1.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 19 16:27:40 2008 " "Info: Processing ended: Thu Jun 19 16:27:40 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}