dds.tan.rpt

基于DDS的数字移相正弦信号发生器设计

; N/A           ; None        ; -10.700 ns ; K[2] ; SUM99:U0|TEMP[4] ; CLK      ;
; N/A           ; None        ; -10.700 ns ; K[5] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -10.800 ns ; K[9] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -10.800 ns ; K[1] ; SUM99:U0|TEMP[2] ; CLK      ;
; N/A           ; None        ; -10.900 ns ; K[0] ; SUM99:U0|TEMP[2] ; CLK      ;
; N/A           ; None        ; -10.900 ns ; K[6] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -11.000 ns ; K[1] ; SUM99:U0|TEMP[3] ; CLK      ;
; N/A           ; None        ; -11.000 ns ; K[3] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -11.100 ns ; K[0] ; SUM99:U0|TEMP[3] ; CLK      ;
; N/A           ; None        ; -11.200 ns ; K[2] ; SUM99:U0|TEMP[2] ; CLK      ;
; N/A           ; None        ; -11.200 ns ; K[3] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -11.400 ns ; K[3] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -11.400 ns ; K[6] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -11.500 ns ; K[1] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -11.500 ns ; K[2] ; SUM99:U0|TEMP[3] ; CLK      ;
; N/A           ; None        ; -11.600 ns ; K[0] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -11.600 ns ; K[6] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -11.800 ns ; K[3] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -11.900 ns ; K[1] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -12.000 ns ; K[0] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -12.000 ns ; K[2] ; SUM99:U0|TEMP[6] ; CLK      ;
; N/A           ; None        ; -12.100 ns ; K[1] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -12.200 ns ; K[0] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -12.200 ns ; K[6] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -12.300 ns ; K[1] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -12.400 ns ; K[0] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -12.400 ns ; K[2] ; SUM99:U0|TEMP[8] ; CLK      ;
; N/A           ; None        ; -12.600 ns ; K[2] ; SUM99:U0|TEMP[9] ; CLK      ;
; N/A           ; None        ; -12.700 ns ; K[1] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -12.800 ns ; K[0] ; SUM99:U0|TEMP[7] ; CLK      ;
; N/A           ; None        ; -12.800 ns ; K[2] ; SUM99:U0|TEMP[5] ; CLK      ;
; N/A           ; None        ; -13.200 ns ; K[2] ; SUM99:U0|TEMP[7] ; CLK      ;
+---------------+-------------+------------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jun 19 16:27:39 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dds -c dds
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 76.34 MHz between source register "REG1:U1|Q[7]" and destination register "ROM:U2|OUTP[4]" (period= 13.1 ns)
    Info: + Longest register to register delay is 11.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_J42; Fanout = 2; REG Node = 'REG1:U1|Q[7]'
        Info: 2: + IC(0.200 ns) + CELL(1.900 ns) = 2.100 ns; Loc. = LC8_J42; Fanout = 1; COMB Node = 'ROM:U2|reduce_or~867'
        Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.000 ns; Loc. = LC1_J42; Fanout = 5; COMB Node = 'ROM:U2|reduce_or~868'
        Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 6.800 ns; Loc. = LC3_J43; Fanout = 1; COMB Node = 'ROM:U2|reduce_or~895'
        Info: 5: + IC(0.200 ns) + CELL(1.200 ns) = 8.200 ns; Loc. = LC4_J43; Fanout = 1; COMB Node = 'ROM:U2|reduce_or~929'
        Info: 6: + IC(0.000 ns) + CELL(1.900 ns) = 10.100 ns; Loc. = LC5_J43; Fanout = 1; COMB Node = 'ROM:U2|reduce_or~900'
        Info: 7: + IC(0.200 ns) + CELL(1.000 ns) = 11.300 ns; Loc. = LC1_J43; Fanout = 1; REG Node = 'ROM:U2|OUTP[4]'
        Info: Total cell delay = 9.400 ns ( 83.19 % )
        Info: Total interconnect delay = 1.900 ns ( 16.81 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J43; Fanout = 1; REG Node = 'ROM:U2|OUTP[4]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_J42; Fanout = 2; REG Node = 'REG1:U1|Q[7]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "SUM99:U0|TEMP[7]" (data pin = "K[2]", clock pin = "CLK") is 14.800 ns
    Info: + Longest pin to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_113; Fanout = 2; PIN Node = 'K[2]'
        Info: 2: + IC(6.400 ns) + CELL(0.700 ns) = 10.500 ns; Loc. = LC6_J20; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 10.700 ns; Loc. = LC7_J20; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 10.900 ns; Loc. = LC8_J20; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 5: + IC(0.900 ns) + CELL(0.200 ns) = 12.000 ns; Loc. = LC1_J22; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 12.200 ns; Loc. = LC2_J22; Fanout = 2; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 7: + IC(0.000 ns) + CELL(1.600 ns) = 13.800 ns; Loc. = LC3_J22; Fanout = 1; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]'
        Info: 8: + IC(1.200 ns) + CELL(1.000 ns) = 16.000 ns; Loc. = LC5_J25; Fanout = 3; REG Node = 'SUM99:U0|TEMP[7]'
        Info: Total cell delay = 7.500 ns ( 46.88 % )
        Info: Total interconnect delay = 8.500 ns ( 53.13 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J25; Fanout = 3; REG Node = 'SUM99:U0|TEMP[7]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "CLK" to destination pin "Q[0]" through register "REG2:U3|Q[0]" is 14.800 ns
    Info: + Longest clock path from clock "CLK" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_J29; Fanout = 1; REG Node = 'REG2:U3|Q[0]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 11.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_J29; Fanout = 1; REG Node = 'REG2:U3|Q[0]'
        Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'Q[0]'
        Info: Total cell delay = 8.600 ns ( 72.88 % )
        Info: Total interconnect delay = 3.200 ns ( 27.12 % )
Info: th for register "SUM99:U0|TEMP[4]" (data pin = "K[4]", clock pin = "CLK") is -5.600 ns
    Info: + Longest clock path from clock "CLK" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 36; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J20; Fanout = 3; REG Node = 'SUM99:U0|TEMP[4]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 8.400 ns
        Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_115; Fanout = 2; PIN Node = 'K[4]'
        Info: 2: + IC(1.800 ns) + CELL(2.000 ns) = 7.200 ns; Loc. = LC8_J20; Fanout = 1; COMB Node = 'SUM99:U0|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]'
        Info: 3: + IC(0.200 ns) + CELL(1.000 ns) = 8.400 ns; Loc. = LC1_J20; Fanout = 3; REG Node = 'SUM99:U0|TEMP[4]'
        Info: Total cell delay = 6.400 ns ( 76.19 % )
        Info: Total interconnect delay = 2.000 ns ( 23.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jun 19 16:27:40 2008
    Info: Elapsed time: 00:00:02